Multi-LMK0482x/LMK04832 SYNC

1. Multi-LMK0482x/LMK04832 SYNC Goals: Understand some theory about synchronization Quickly discuss the main points of JESD204B Subclass 1 and clocking See different techniques to SYNC multiple LMK devices

2. Introduction of Phase Uncertainty • Any divide introduces other possible phases

3. Introduction of Phase Uncertainty SYNC • Any divide introduces other possible phases SYNC Event

4. Introduction of Phase Uncertainty SYNC • Any divide introduces other possible phases SYNC Event

5. Marking an edge for a divider in JESD204B

6. About JEDEC and JESD204B • JEDEC is a standards group which defined standard JESD204B • JESD204B is a definition for data converters to allow synchronization of data between data converters and logic devices. • “This specification describes a serialized interface between data converters and logic devices. It contains normative information to enable designers to implement devices that communicate with other devices covered by this specification. Informative sections are included to clarify and exemplify the specification.”

7. Synchronization in a PLL • Non-integer divide ratios require R-divider resets. N=16 R=4 N/R=4 No Reset Required N=16 R=6 N/R=2.6̅6 Reset Required

8. Synchronization in a PLL • N/R = 16/6 = 2.6̅6 • Must reset R divider in this case!

9. Clock Distribution: With and Without 0-Delay Clock Distribution Device without 0-Delay Clock Distribution Device with 0-Delay • 0-delay includes the divider in the feedback path for comparison/alignment with the reference clock

10. 0-Delay Rules for Deterministic Phase Relationship • 1st Rule, the GCD between input and output frequency must equal input frequency • GCD(CLKin_FREQ, CLKout_FREQ) == CLKin_FREQ • 2nd Rule, lowest output frequency requiring determinism used for 0-Delay feedback • When multiple outputs require determinism, the frequency must be the GCD(Freq1, Freq2, …, FreqN) • This is the frequency which then must be used as clock output frequency for 1st Rule. • CLKout_FREQ = GCD(CLKout1_FREQ, CLKout2_FREQ, … , CLKoutN_FREQ)

11. Example of 0-Delay Timing in Clock Device • Phase detector will align reference with phase of PLL N / 4 • Since N / R = 1, only one valid alignment • Output is deterministic

12. Example of 0-Delay Timing in Clock Device • N / R = 2.6̅6, so R-divider reset is required to establish deterministic phase

13. 0-Delay and JESD204B Clocking (Divider Reset) • 0-Delay cancels phase uncertainty in divided output by making a phase comparison of divided output with input to line them up with the PLL loop. • Closed loop: 0-delay aligns itself, as long as 0-delay rules are obeyed • A JESD204B SYSREF divider reset eliminates phase uncertainty by telling a divide when to start dividing (or counting). • This is how JESD204B sub-class 1 achieves deterministic latency. • The SYSREF signal is the divider reset. It synchronizes the divider. In JESD204B words, the LMFC (local multi-frame clock) divider is reset (along with other dividers, depending on implementation) • Another way to think of JESD204B SYSREF divider reset is like Open Loop 0-Delay.

14. Consequences of 0-Delay Rules • With 100 MHz and 125 MHz outputs, 25 MHz must be feedback for 0-delay. • 10 MHz reference is too high for determinism, must be 5 MHz at phase detector • Loop bandwidth, phase noise impacted when outputs relate poorly to inputs

15. LMK Reset Path for Divider Synchronization • SYNC/SYSREF distribution path is shared with divider reset path • SYNC_DISxmuxes gate SYNC/SYSREF distribution path (SYSREF_CLKin0_MUX output) to divider reset • When SYNC_DISxmuxes are disabled, SYNC/SYSREF signal is distributed to output muxes • When SYNC_DISxmuxes are enabled, SYNC signal forces affected outputs low until SYNC signal is deasserted (because dividers are held in reset)

16. Relationship between Device Clock and SYSREF C = SYSREF_DIV_ADJUST + DCLKout_MUX_ADJUST

17. Cases for Multi-LMK SYNC

18. Case 1: Bad News No PLL, Good News No PLLNo PLL tricks, but no PLL phase uncertainty either!

19. Frequency Paths in Distribution Mode

20. LMK Divider Reset Paths in Distribution Mode

21. Pulsed SYSREF in Distribution Mode

22. Case 2a/2b: When Things Are SimpleReference Frequency == SYSREF Frequency

23. Cases 2a/2bSynchronization using 0-delay with SYSREF frequency • Benefits: • Simple • Consequences: • Must use SYSREF asreference frequency • If not using dual PLL,jitter performance couldbe degraded by newconstraints on loopbandwidth, phase detector frequency

24. Case 3a/3b: Good Enough?Trying to do divider reset for synchronization against a 3-GHz VCO

25. Case 3a: Divider Sync Configuration

26. Case 3a/3b: Setup and Hold Time • Valid Window is about 200ps • “Bullseye”

27. Importance of ±0 Cycle Error for SYSREF Signal? • The point of JESD204B is determinism, so it’s fair to insist on it. • But what qualifies as deterministic is application dependent • Any error is only a digital buffer shift away from correction… but figuring out when to perform this shift, and by how much, is also a hard problem!

28. Case 4a/4b: Being CleverRe-clocking SYSREF with 0-Delayed Clock

29. Reminder: Case 3a, Divider Sync Configuration

30. Case 4a: Re-clock SYNC to the Feedback Divider

31. Reminder: Case 3a, Setup and Hold Time

32. Case 4a: Setup and Hold Time Are Much Easier!

33. Case 5a/5b: In ProgressStill considering effects of PLL1 phase detector skew