PAMA Power Aware Multiprocessing Architecture

1. PAMAPower Aware Multiprocessing Architecture Dong-In Kang, dkang@isi.edu now at USC/ISI Was at CS dept. of

2. Power Aware Network Power Aware Node Motivation / Problem Statement • High processing requirements, power-constrained, e.g. • Space-based processing • UAV(Unmanned Air Vehicle) • Current strategy: constrain maximum power consumption • Does not consider energy storage, dynamic processing requirements • PAMA mission: • Power management techniques at run-time • System synthesis technique for power-efficient system

3. Opportunities in Multiprocessing • Processing power can be dynamically managed in multi- dimensions: • processing per node (clock/voltage scaling) • number of processors • Interconnection topology and width • Interprocessor communication vs. processing trade-off is interesting • Communication is important power consumer but not prohibitive • Memory allocation can be managed for power

4. PAMA Goals • Demonstrate power management techniques on COTS multiprocessor hardware • Develop platform for power management experiments • Develop power management software library • Develop power aware system synthesis technique/tool

5. PAMA Architecture

6. Initial PAMA Implementation

7. 8 7 @ 20 MHz Power (W) @ 10 MHz 6 @ 5 Hz 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 # of processors running Experiments • Parameter values • Frequency: 20 MHz – 80 MHz (internal core frequency) • Number of processors: 0 - 8 • Results • Performance: 0 MIPS - 640 MIPS • Power variation • Total Power: 1.44 W – 7.24 W

8. Interconnection Power Consumption • Ring vs. Crossbar (8 processors, FPGA implementation) • Ring consumes more power than crossbar (surprise!) • Dependent on number of nodes • Implementation-dependent, control signal buffering • Variation between topologies greater than between different amounts of communication

9. XA XB XC4085 XC4085 FPGA FPGA SRAM SRAM Running PAMA Application M32R/D M32R/D M32R/D M32R/D M32R/D M32R/D M32R/D M32R/D CLK IF XC4062 FPGA EEPROM PC Debugger PIM Program Control Programs

10. Power Control Unit … Power-Aware Node N-1 Power-Aware Node 0 Power Aware Interconnection Network CPU RAM CPU RAM Next Generation PAMA • More powerful and power-aware processor • Internal clock speed and supply voltage control • More intelligent power control unit • Better software environment • Embedded Linux, MPI

11. 8x 80x Case Study • M32R/D vs. StrongArm : • Each node has dynamic power range of 10 in running node • Board provides dynamic power range of 40-80 depending on # of nodes/board • Increases processing power by factor of 4 • Increases memory capacity by factor of 16 • Increases I/O bandwidth by factor of 6

12. Synthesis Technique • Constraints • Battery Life (static, dynamic) • Throughput requirement • Latency • System configuration • Network topology, Processing power, etc. • Application description • Goal • Performance/Power consumption prediction • Static/Dynamic optimal performance and energy trade-off