Toward Quantifying the IC Design Value of Interconnect Technology Improvement

1. Toward Quantifying the IC Design Value of Interconnect Technology Improvement Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li VLSI CAD LABORATORY, UC San Diego http://vlsicad.ucsd.edu

2. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

3. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

4. Motivation • Wire delay increases with technology scaling • Improvement of BEOL both important and expensive • Issue 1: no systematic quantification of ROI from BEOL improvement • Issue 2: unclear whether BEOL improvement benefits can be leveraged by EDA tools • Goals: • A framework to quantify BEOL improvement values guide BEOL technology investment and targets • Assess EDA tools’ ability to leverage improved BEOL = potential “EDA gap”

5. Focus of Our Work • Product quality comes from interaction among design, BEOL technology, EDA tool • We focus on interaction between BEOL and EDA This work EDA tool BEOL Technology Design

6. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

7. Related Work • Studies of DRAM or simple logic circuits, not at chip-level • Ignores interaction between BEOL technology, EDA tool • [Li01] – DRAM performance improvements from low-k • [Kapur02]– R, C impacts on signal, power • [Bamal06] – Performance, energy comparison studies with different interconnect technologies • Focus on variation, not future BEOL improvements • [Jeong10] – Chip-level impacts of interconnect variation due to double-patterning

8. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

9. Our Framework • Modify BEOL files to model R, C reductions in future technologies • Modify ITFfiles • Use Synopsys StarRC to convert ITFto TLUplusfiles • Design implementation (RTL-to-layout and signoff) with original and modified BEOL files • Run timing, power analysis Original BEOL files Hypothetical RC reductions Modified BEOL files Designs Circuit implementation flow (synthesis, place and route) Circuit implemented with original BEOL Circuit implemented with modified BEOL Timing and power analysis

10. Testbed • Designs: {aes_cipher, des_perf, mpeg2, pci_bridge32} from OpenCoresx{fast, slow} clock periods • Technology: TSMC 45nm, LVT and HVT • 20SOC and below can be very different • SP&R: Synopsys Design Compiler + IC Compiler • Execute each P&R run three times denoising • Timing and power analysis: Synopsys IC Compiler • Signoff: no hold or EM violation, TNS < 30ps Apples-to-apples comparison for design metrics

11. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

12. Expt 1: Impact of R, C Reduction on Power • 45% R, C reduction only leads to 8% power reduction • R, C reduction improves timing  fewer / smaller cells  leakage power ↓ (but, only on critical paths) • C reduction  load cap ↓  net switching power ↓(but, gate cap dominates) Power of implementation with original BEOL R, C=α%: implementation with α% dielectric constant and metal resistivity w.r.t original BEOL R, C reduction occurs on M2-M5

13. Impact of R, C Reduction on Area • R, C reduction leads to little improvement in area • Tool uses Vtswapping to exploit improved timing • Same footprint of LVT and HVT cells  same post-opt area • Optimization methodology of EDA tools affects value extracted from improved BEOL Area of implementation with original BEOL

14. Expt 2: Reduction in R vs. in C • In this experiment, C reduction offers more benefits • Wire delay↓  trade timing for power • R reduction improves wire delay • C reduction improves wire delay + load cap • R reduction can be critical with high Vdd, temperature • Technology R&D might focus more on C reduction Power w/ only R reduction Power w/ only C reduction

15. Expt 3: R, C Reduction in Advanced Technology • Wire delay becomes critical in advanced technologies • Impact of R reduction increases • We model advanced technology = increase R by 8x • Benefits of R, C reduction increase in advanced technologies Leakage power Total power 5% Advanced Current Advanced Current 2%

16. Expt 4: Impact of Layer Selection • BEOL improvement incurs high manufacturing cost • What is optimum subset of layers to improve under cost limits? • Flexible BEOL = subset of layers is selectively improved • Inappropriate selection of R, C-reduced layers is suboptimal • Guideline: reduce R, C on adjacent and highly utilized layers • Small difference between different layer selections • Tools’ ability to leverage the improved BEOL layers? RC-reduced layers are far from each other RC reduction has more benefit on highly utilized layers Layers with improved BEOL

17. Tools’ Exploitation of R, C Reduction • Assessment flow • Implement designs with both original and improved BEOL • Run timing and power analysis with improved BEOL • Compare frequency, power • Preliminary results show tool can leverage R, C reduction • Case 1 might be misguided during optimization Case 1: Implementation with original BEOL, analyzed with modified BEOL Case 2: Implementation with modified BEOL, analyzed with modified BEOL Reduced R, C on M2, M5 Reduced R, C on M3, M4

18. RC-Awareness in EDA Tools • A “smart” router should be aware of improved BEOL • Route setup critical paths on layers with small R, C • Route hold critical paths on layers with large R, C • ∆wire distribution (of layer x) = %wire on layer x - %wire on layer x • Assessment: • Implement designs with flexible BEOL • Check ∆wire distribution of layers for setup- and hold-critical nets w/ improved BEOL w/ original BEOL

19. Experimental Results M2 ∆Wire distribution • Compare ∆wire distribution from current router (bars) and a hypothetical RC-aware router (ovals) • White (Orange) = positive (negative) ∆wire distribution • Same color of bar and dotted oval  RC-awareness • Router is not fully responsive to BEOL R, C reduction M3 M4 √ √ √ √ √ X X X Setup-critical nets Hold-critical nets M5 √ X X X √ √ X X {2,3,4,5} {2,3} {2,4} {2,5} {3,4} {3,5} {4,5} {2,3,4,5} {2,3} {2,4} {2,5} {3,4} {3,5} {4,5} Layers with reduced RC Layers with reduced RC X √ X X √ √ √ √ X X √ X X √ √ X

20. Outline • Motivation • Related Work • Our Framework • Experiments and Results • Conclusion

21. Conclusion • Framework to quantify impact of interconnect resistance and/or capacitance reductions on chip-level design metrics • Reduction in capacitance gives more benefits than in resistance • R reduction can be critical in wire-delay dominant designs (due to high Vdd, temperature or advanced technology) • Capability of EDA tools to leverage improved BEOL has room for improvement • Ongoing works • Iso-constraints vs. iso-GDS

22. ISO-GDSExpt • Basic tradeoffs to exploit improved BEOL • R, C reduction  improved timing  Vdd↓  Power ↓ Vdd reduction Activity factor + nominal voltage + device type Performance requirement + device type Power reduction R, C reduction Frequency improvement Gate-wire balance R, C reduction R, C reduction

23. Conclusion • Framework to quantify impact of interconnect resistance and/or capacitance reductions on chip-level design metrics • Reduction in capacitance gives more benefits than in resistance • R reduction can be critical in wire-delay dominant designs (due to high Vdd, temperature or advanced technology) • Capability of EDA tools to leverage improved BEOL has room for improvement • Ongoing works • Iso-constraints vs. iso-GDS • Study impact of interconnect R, C reduction across wide supply voltages • Extend our analyses to M1 and middle-of-line layers

24. Acknowledgments • Work supported from Sandia National Labs, Qualcomm, Samsung, NSF, SRC, the IMPACT (UC Discovery) and IMPACT+ centers

25. Thank You!

26. Backup Slides

27. Values of Improved BEOL • Question 1: What is overall impact of R and/or C reduction(s) on design metrics? • 45% R, C reduction  8% power reduction, similar area • Question 2: Which reductions offer more benefits, in R or in C? • C reduction offers more benefits • R reduction can be critical with high Vdd, temperature • Question 3: How will impacts of R, C reduction change in advanced technology nodes? • Benefits of R, C reduction increase in advanced technology • Question 4: What is optimum subset of layers to improve under cost limits? • Should reduce R, C on adjacent and highly utilized layers