Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation

1. Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: Energy: Average Power: Power and Energy

3. Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND This repeats Tfsw times over an interval of T Dynamic power

4. Vdd Vin Vout C L Energy stored at the capacitor at the end of 1  0 transition: dissipated in NMOS during discharge (input: 0  1) Dynamic power dissipation load capacitance (gate + diffusion + interconnects) Energy delivered by the supply during input 1  0 transition:

5. Capacitive dynamic power • If the gate is switched on and off f01 (switching factor) times per second, the power consumption is given by • For entire circuit where αi is activity factor [0..0.5] in comparison to the clock frequency (which has switching factor of 1)

6. When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are comparable for input and output Short circuit current

7. Dynamic power breakup Total dynamic Power [source: Intel’03]

8. 200 Mtransistor chip (1.2 V 100 nm process Cg = 2 fF/mm) 20M logic transistors Average width: 12 λ 180M memory transistors Average width: 4 λ Calculating dynamic power: An example • Static CMOS logic gates: activity factor = 0.1 • Memory arrays: activity factor = 0.05 (many banks!) • Estimate dynamic power consumption per MHz.

9. Static power is consumed even when chip is quiescent. Leakage draws power from nominally OFF devices Static (leakage) power

10. The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: 20 nA/mm for low Vt 0.02 nA/mm for high Vt Gate leakage: 3 nA/mm for thin oxide 0.002 nA/mm for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic Leakage example

11. Estimate static power: High leakage: Low leakage: Leakage power (continued) • If no low leakage devices, Pstatic = 749 mW (!)

12. Reduce dynamic power a: clock gating, sleep mode C: small transistors (esp. on clock), short wires VDD: lowest suitable voltage f: lowest suitable frequency I1 O1 I2 Clock I3 I4 O2 Enable I5 I6 critical path Clock Gating only reduce supply voltage of non critical gates Techniques for low-power design

13. Scaling down supply voltage reduces dynamic power reduces saturation current  increases delay  reduce the frequency Dynamic power reduction via dynamic VDD scaling Dynamic voltage scaling (DVS):Supply and voltage of the circuit should dynamic adjust according to the workload of our circuits and criticality of the tasks

14. Reduce static power Selectively use low Vt devices Leakage reduction: - stacked devices, body bias, low temperature Reducing static power

15. Leakage depends exponentially on Vth. How to control Vth? Remember: Vth also controls your saturation current  delay 2. Oxide thickness 1. Body Bias Sol1: statically choose high Vt cells for non critical gates I1 O1 I2 I3 I4 O2 I5 I6 critical path Leakage reduction via adjusting of Vth • Sol2: dynamically adjust the bias of the body • idle: increase Vt (e.g. by applying –ve body bias on NMOS) • Active: reduce Vt (e.g.: by applying +ve body bias on NMOS)

16. Leakage reduction via Cooling • Impact of temperature on leakage current

17. We are still in chapter 4: We covered delay and power estimation Next time, we going to move into integrating the impact of wires into delay/power calculations Summary