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EECS579 Term Project

EECS579 Term Project. Low Power Testing Feng Wang. why low power testing?. Testing mode consumes more power than operating mode. Low input vector correlations More activity than operating mode Test on uncompleted chip—heat accumulates. B are die testing Causing problems:

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EECS579 Term Project

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  1. EECS579 Term Project Low Power Testing Feng Wang

  2. why low power testing? • Testing mode consumes more power than operating mode. Low input vector correlations More activity than operating mode • Test on uncompleted chip—heat accumulates. Bare die testing • Causing problems: Cost, circuit destruction, reliability, battery life, • Now a days, more need: testing speed increased circuit scale decreased circuit density increased

  3. Power model Peak power Average power Static Dynamic current drawn continuously from the power supply • short-circuit current, • charging and discharging Pi =1/2siFic0V2DD P =1/2siFic0V2DD

  4. Power Model • Based on the scan chain transition model Pd = 1/2 C V2DD NG f *NG the total number of gate output transitions (1/0 or 0 /1) *f the repetition frequency. PR(ti) power dissipated in scan latches due to scan in and scan out of vector ti; PCR(ti,tj) power dissipated in combinational circuit C during the scan test; • Based on the consideration of signal activity and test length, gives an average power model:

  5. Techniques and approaches to solve the testing power problem Already practiced in industry • Oversizing power supply • Improve package and cooling • Reduce the test frequency Problems • Increased hardware cost • Increased test time • Decreased fault coverage

  6. Techniques and approaches to resolve the testing power problem State of art approaches • Test Scheduling Algorithms • Low Power ATPG • Circuit Partitioning • Lower Power BIST test pattern generation • Test vector order • Scan latch modification and reordering • Test vector compaction and filtering • Clock Scheme modification • More…

  7. Test Vector ordering and Scan Latch ordering Optimize the test vector propagating sequence in latches for best test power Total transition graph for a certain circuit • The edges’ weight represents the transition number when one vector changes to the other. • Find the path that goes over all the nodes and have a minimum sum of weight.

  8. Test Vector ordering and Scan Latch ordering • Different latch ordering result in different transition number. Find the best one for optimal power. Test Vector (0100,0111) Latch ordering F1,F2,F3 Test Vector (0100,0111) Latch ordering F1,F3,F2

  9. Scan Chain Modification Insert logic gates between scan latches to remove the ripple during scan in/out Impact Motivation • Insertion of XOR/INV remove the transitions. • Resultant test vectors in the latches are unchanged • Need to modify the test input accordingly. • Use basic 3-block, 2 gates insertion. • For a scan chain with n latches, there are n-2 blocks need to be considered. • An overall optimization is needed with some algorithm.

  10. a.  PI change ASAP b. PI change at time t1 a.   PI change ALAP b. PI change at time t2 Primary input freezing Optimize the change time of PIs so that the transition number in the scan chain is minimized and so the power dissipation is optimized.

  11. Multiple scan chains--a clock scheme modification Grouping scan latches so that each group can use an extra PI vector to eliminate the spurious transitions {S0, S1} are incompatible {S2, S3} {S4, S5} are compatible DFT architecture based on multiple scan chains

  12. Scan Array solutions Reduce the test power by reducing the Rate of Bit Propagation(RBP) Traditional RBPc = N(N+1)/2; SA RBPa = N(H+1)/2+N(L+1)/2; When H is far less than L, then RBPc = H * RBPa

  13. Low power testing by “don’t_care Identification” For a given test input set, identify an Xs set from the input such that the vectors providing peak power have more Xs than others. Because the X inputs can take an arbitrary logic value without losing fault coverage, we then reassign a logic value to them such that switching activity of the circuit is decreased. Reassignment Rules • The scan-latch order is not changed, i.e., a scan-latch order determined with timing and layout constraints is allowed. • The number of test vectors is not increased even when the given test set has been generated using test compaction techniques. • The test set obtained keeps the same fault coverage for single stuck-at faults as the original one. • Modification of ATPG algorithms is not required because the proposed method is applied to a generated test set.

  14. Low power ATPG 1) Cost functions are calculated for every line in the CUT and the fault that has the minimum transition test generation cost, among the faults that belong to the fault list, is selected as the next target fault. 2) The proposed PODEM is used to generate a vector that detects the target fault with a minimum number of transitions.If the fault is found to be undetectable, then it is dropped from the fault list. 3) If the vector has any don’t care bits, then the procedure don’t_care() is used to assign appropriate binary values to these bits. 4) Faults detected by the vector are dropped from the fault list. 5) Steps 1 to 4 are repeated until no faults remain in the fault. • Use the controllability cost and to guide the backtrace. • Use the observability cost to select D-frontier for fault propagation. • Use a new procedure, called don’t_care(), to assign an appropriate value to each don’t care bit.

  15. Low power BIST by test vector filtering and reseeding test vector filtering:Analyze the test sequence, find out the non-detecting sequences and inhibit these sequences. reseeding: Load the LFSR with different seeds so that the hard-to-test faults can be covered with reasonable length of test sequence. Non-detecting sequences Architecture of filtering algorithm Architecture of reseeding algorithm

  16. Hardware for RISC generation Generation principle of RISC test sequence RSIC test generation for low power testing In a RISC(random single-input change) sequence, the correlation between consecutive test vectors is high compared with RMSC (random multi-input change). This reduces the transitions that happen in the circuit when test patterns change and so result in low power testing.

  17. Efficiency of different approaches

  18. Summary • Low power testing is important • The existing techniques are not enough • New techniques with novel idea have been raised • Different approaches are applicable to different kinds of circuits • Trade-offs always come with the power reduction • Some techniques are orthogonal and can be used on the same circuit for better optimization

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