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Chapter 6. Arithmetic. Addition. Carry out. 7 + 6 13. Carry in. 0 1 1 1 + 0 0 1 1 1 1 0 0 0 1 1 0 1. Carry-in. Carry-out. Sum. c. x. y. s. c. i. i. i. i. i. +1. 0. 0. 0. 0. 0. 0. 0. 1. 1. 0. DNF (disjunctive normal form). 0. 1. 0.
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Chapter 6 Arithmetic
Addition Carry out 7 + 6 13 Carry in 0 1 1 1 +0 0 1 1 1 1 0 0 0 1 1 0 1
Carry-in Carry-out Sum c x y s c i i i i i +1 0 0 0 0 0 0 0 1 1 0 DNF (disjunctive normal form) 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 x y c + x y c + x y c s + x y c + + = x y c = i i i i i i i i i i i i i i i i y c x c x y c + + = i i i i i i i +1 Figure 6.1.Logic specification for a stage of binary addition.
yn-1 y0 y1 xn-1 x0 x1 c1 Cn-1 … c0 FA cn FA FA sn-1 s0 s1 Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder
yn-1 y2n-1 Xn-1 ykn-1 y0 Xn X2n-1 yn Xkn-1 X0 … … cn Cn-1 … n-bit adder n-bit adder n-bit adder c0 ckn … … skn-1 S(k-1)n s0 S2n-1 Sn-1 Sn Cascade of k n-bit adders
y y y n - 1 1 0 … Add/Sub control x x x n - 1 1 0 … … n -bit adder c n c 0 … s s s n - 1 1 0 Figure 6.3. Binary addition-subtraction logic network
Timing inputs yn-1 y0 y1 Xn-1 X0 X1 c1 Cn-1 … c0 FA cn FA FA sn-1 s0 s1 result Least significant bit (LSB) position Most significant bit (MSB) position N-bit ripple carry adder
Timing • Gate delays • Propagation through the circuit over the longest path • From x0 …y0 at the LSB position • To cn, Sn-1 at MSB • Cn-1 available in 2(n-1) “gate delays” • Sn-1 available 1 delay later • Cn 1 delay later • Total of 2n gate delays • + 2 more to set overflow
1 “gate delay” 2 “gate delays” Logic for a Single Stage
2(n -1) gate delays to here yn-1 y0 y1 Xn-1 X0 X1 c1 Cn-1 … c0 FA cn FA FA sn-1 s0 s1 1 more gate delay to here Least significant bit (LSB) position Most significant bit (MSB) position 1 more gate delay to here 2n gate delays + 2 more to set “overflow” N-bit ripple carry adder
Timing • 2 n gate delays: n = 8, 32, 64 • Need for “fast adder” • Carry lookahead
x y c + x y c + x y c s + x y c + + = x y c = i i i i i i i i i i i i i i i i y c x c x y c + + = i i i i i i i +1 ci+1 = xi yi + (xi + yi) ci ci+1 = Gi + Pi Ci where Gi = xi yi and Pi = xi + yi (G = “generate” P = “propagate”) ci+1 = Gi + PiGi-1+ PiPi-1 ci-1 … ci
Then, the expression for any carry is: ci+1 = Gi + Pi Gi-1 + Pi Pi-1Gi-2 + … + Pi Pi-1…P1G0 + Pi Pi-1 …P0C0 For a 4-bit adder: c0 = G0 + P0 c0 c1 = G1 + P1 G0 + P1P0 c0 c2 = G2 + P2 G1 + P2P1 G0 + P2P1P0 c0 c3 = G3 + P3 G2 + + P3P2 G1 + P3P2 P1G0 + P3P2P1P0 c0
= + + x y c i i i Gi = xi yi Pi = xi + yi + Same as Unless xi + yi = 1 and then Gi = 1 and it doesn’t matter what Pi is x y i i Bit-stage cell
4-bit carry-lookahead adder The “calculation” from the preceding chart 4 bits => “fan-in to last (left-most) gate is 5 -- the limit for practical application
x y x y x y x y 15-12 15-12 11-8 11-8 7-4 7-4 3-0 3-0 . c c c 12 8 4 c 4-bit adder 4-bit adder 4-bit adder c 4-bit adder 16 0 s s s s 15-12 11-8 7-4 3-0 I I I I I I G P G P G P G I P I 3 3 2 2 1 1 0 0 Carry-lookahead logic II II G P 0 0 Figure 6.5. 16-bit carry-lookahead adder built from 4-bit adders (Similarly for 32-bit or 64-bit adders)
Multiplication of Positive Numbers (13) Multiplicand M 1 1 0 1 x 1 0 1 1 (11) Multiplier Q 1 1 0 1 1 1 0 1 0 0 0 0 1 1 0 1 (143) Product P 1 0 0 0 1 1 1 1 Multiply “by hand” or programmatically (a) Manual multiplication algorithm
Uses lots of gates (transistors), lots of space on a chip (64 x 64, say) Delay--signal propagation from upper right to lower left--for an n x n array: 6(n-1) gate delays
Register A (initially 0) Shift right q0 a0 C qn-1 an-1 Multiplier Q Add/Noadd control n-bit adder Control Sequencer MUX 0 0 mn-1 m0 Multiplicand M Sequential circuit binary multiplier (positive numbers)
Multiplicand in M, Multiplier in Q, • A initially 0, C initially 0 • C is the carry from the adder • C, A and Q combined will hold the partial product • LSB in Q will determine the Add/Noadd to determine if M is to be added to the partial product • C, A and Q are shifted right after each add so LSB in Q always hold next multiplier bit (previous LSB is discarded) • Control sequencer will shift and add n times
13 x 11 M 1101 0 0000 1011 Initial configuration C A Q 0 1101 1011 Add 0 0110 1101 Shift 1 0011 1101 Add 0 1001 1110 Shift 0 1001 1110 Add 0 0100 1111 Shift 1 0001 1111 Add 0 1000 1111 Shift First cycle Second cycle Partial product Third cycle Fourth cycle Product 143
Signed Operands • Positive multiplier and a negative multiplicand: • partial product must be sign extended (to the left as far as possible) Maintains the sign of the partial product
1 0 0 1 1 ( -13) 0 1 0 1 1 (+11) 1 1 1 1 1 1 0 0 1 1 Sign extension is shown in red 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 (-143) 1 1 0 1 1 1 0 0 0 1 Figure 6.8.Sign extension of negative multiplicand.
Signed Operands • Negative multiplier: • Replace both numbers with their two’s complement (doesn’t change the sign of the result) Proceed as before Just add sign extension hardware to what was discussed for positive numbers
Register A (initially 0) Shift right q0 a0 C qn-1 an-1 Multiplier Q Add/Noadd control n-bit adder Control Sequencer MUX 0 0 mn-1 m0 (always positive) Multiplicand M Maintain a sign-extended partial product Sequential circuit binary multiplier (signed numbers)
0 1 0 1 1 0 1 0 0 + 1 + 1 + 1 + 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 Figure 6.9.Normal multiplication scheme.
Multiplier 0011110 requires adding 4 shifted versions of the multiplicand 0011110 (30) can also be viewed as the difference between two numbers (32 and 2) 0100000 (32) - 0000010 (2) 0011110 (30)
0 1 0 1 1 0 1 + 1 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2's complement of the multiplicand 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 Figure 6.9.Booth multiplication scheme.
0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 Figure 6.10.Booth recoding of a multiplier.
Multiplier V ersion of multiplicand selected by bit i i - Bit i Bit 1 0 0 0 ´ M 0 1 + 1 ´ M 1 0 1 ´ M 1 1 0 ´ M Figure 6.12.Booth multiplier recoding table.
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Worst-case multiplier + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 + 1 - 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0 Ordinary multiplier 0 - 1 0 0 + 1 - 1 + 1 0 - 1 + 1 0 0 0 - 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 Good multiplier 0 0 0 + 1 0 0 0 0 - 1 0 0 0 + 1 0 0 - 1 Figure 6.13.Booth recoded multipliers.
1101 13 21 10101 274 100010010 26 1101 14 10000 13 1101 1 1110 1101 1 Figure 6.20. Longhand division examples.
Shift left Dividend Q Quotient setting Add/Subtract n-bit adder Control Sequencer Divisor M Circuit for binary division
Division n times: • 1) Shift A and Q left 1 • 2) Subtract M from A, result in A • 3) • if sign of A is 1, set q0 to 0 and add M back to A (restore A • otherwise set q0 to 1
Floating Point Representation • Need for more than just (say) 32-bit integers • Need larger numbers • Need fractions (some very small) • Integers • d31, d30, …. d0. The binary point or • . d31, d30, …. d0 The binary point
Floating Point Representation • Neither is satisfactory • Need the binary point to “float” • Scientific notation • .12345 1.234 x 10-2 • 1234.5 1.234 x 103 • 12.345 1.234 x 10
binary point An E of 0 means 2-127 E of 127 means 20 E of 255 means 2128 IEEE standard (Intel and other processors conform)
Normalization and the “hidden bit” 0 0010110… Unnormalized: 10001000 0.0010110… x 29 1.0110… x 26 Normalized: 0 010110… 10000101 the “hidden bit” (always a 1)
Single precision: ~7 decimal digits of “precision” (7 significant digits) in range 2-127 to 2128 (or 10-38 to 1038 ) Double precision: ~16 decimal digits in range 2-1022 to 21023 (or 10-308 to 10308 )
Special Values • E = 0 M = 0 value is 0 • E = 255 M = 0 value is “infinity” (result of divide by 0) • E = 0 M /= 0 “denormal numbers” smaller than the smallest “normal number” gradual underflow • E = 255 M /= 0 NaN result of an invalid operation(undefined) e.g., 0/0, sqrt(-1)