Virtual Platform Development for Embedded Software Optimization

1. Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study Sungpack Hong , Sungjoo Yoo , Sheayun Lee , Sangwoo Lee , Hye Jeong Nam Bum-Seok Yoo , Jaehyung Hwang , Donghyun Song , Janghwan Kim , Jeongeun Kim , HoonSang Jin , Kyu-Myung Choi , Jeong-Taek Kong , SoKwan Eo CODES+ISSS '06

2. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

3. Introduction(1/2) • Virtual platform(ViP) • is one of the most widely renowned system level design techniques. • ViP development • ARM-ESL SocDesigner, ConvergenSC, Magillem ,Cocentric System Studio • Modeling standards • SystemC

4. Introduction(2/2) • Objective • Report an industry case study of applying the ViP technique to real product development • Practical issues for ViP development • SW optimization based on the ViP

5. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

6. Overview(1/5) • Target System: Hybrid HDD(Hard Disk Drive) • A large-sized flash memory is attached to a legacy disk drive as a non-volatile(NV)cache. • First advantages • The NV cache reduces mechanical movement of the disk, thus enabling reduction in the power consumption of HDD. • Second advantages • Reduces since seek and rotation delay of the legacy HDD.

7. Overview(2/5) • Required Design Changes • HW • NV cache related data-path had to be added to the existing HDD controller LSI, including a controller for OneNAND flash memory • FW • Had to manipulate additional tasks having more complexity e.g. Managing consistency of data spread over disk, SDRAM, and flash.

8. Overview(3/5) • There were three challenges in the development of hybrid HDD • How to increase system performance? • How to verify architectural decisions? • How to accelerate FW development?

9. Overview(4/5) • ViP objectives • To measure system performance and analyze its bottlenecks(successfully) • To find out possible optimization points from the result of bottleneck analysis(successfully) • To evaluate various architectural decisions of both HW side and FW side at the early stage of development(successfully) • To provide an early-access platform for FW development ahead of chip fabrication(not so satisfactory) • To exploit other advantages of ViP like co-verification as much as possible(not so satisfactory)

10. Overview(5/5) • Early Software Development and Optimization

11. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

12. ViP Development(1/7) • General Issues on ViP Development • Timing accuracy • Accurate enough to analyze system performance including HW-SW interaction • Simulation speed • Be fast enough to execute whole FW for meaningful time • Development time • Be available earlier than real-chip environment

13. ViP Development(2/7) • Limiting Modeling Scope for Early Development • Do only the least of what you have to do • Physical and link layer activities of SATA communication were just replaced with simple timed data-copy routines in the model. • Only selected set of registers are implemented in the ViP(only 30% of registers were sufficient to be modeled for FW execution)

14. ViP Development(3/7)

15. ViP Development(4/7) • Using different Timing Accuracy

16. ViP Development(5/7) • Chose appropriate HW affinity

17. ViP Development(6/7) • Automatic Model Creation • Advantages • Highest affinity to RTL • Fast model creation free from human error • No demand for knowledge on the RTL code • Disadvantages • Not applicable to some blocks • Slower than pure ESL model(this case degraded around 45%) • The generated model has signal interfaces only

18. ViP Development(7/7) • Modeling External Components • Memory device • Functional (un-timed) model; its timing behavior is solely controlled by the memory controller which was modeled with full cycle-accuracy • Host device • Plays the role of input-pattern generator; it reads a script file and, in timely manner, generates a stream of ATA commands to the virtual host-interface model.(replaced with simple function calls) • Disk model • Used a simple linear equations to calculate seek and rotational delay • 1

19. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

20. Software Optimization based on the ViP(1/3)

21. Software Optimization based on the ViP(2/3) • ViP can provide enough time accuracy for bottlenck analysis(either in HW or SW side)

22. Software Optimization based on the ViP(3/3) • Firmware Optimization Techniques • Algorithmic Optimization • Latency Hiding • Pipelining • DMA Access • Memory Relocation • Data Structure Modification • Hardware Modification

23. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

24. Requirements for future ESL Technology(1/2) • ViP needs to be available much earlier than in the current practice if it is for an early-access platform • Simulation speed needs to be significantly improved for FW development • System optimization cycle accuracy should not be sacrificed

25. Requirements for future ESL Technology(2/2) • First create a fast-running model then replace it with slow-but-accurate one later • A part of custom RTL design is synthesized into an FPGA while its execution is synchronized with top-level ESL-simulation.

26. Outline • Introduction • Overview • Virtual Platform Development • Software Optimization based on the ViP • Requirements for future ESL Technology • Conclusion

27. Conclusion • Creating the ViP of a SoC and exploiting it for a real product development,especially for FW optimization. • Improving system performance by more than 50%