Pre-Processing Filter for Audio Applications

1. Pre-Processing Filter for Audio Applications By Nathan Shaw, Lerzan Celikkanat, and Xiangfeng Wang ELEC 422 VLSI Design 1 Fall 2005

2. Overview • Implementing a low pass FIR filter • 4 taps • 8-bit I/O, Two’s Complement • Major Components: • FIFO • 8-bit multiplier • 16-bit adder • PLA: control unit/ROM

4. Filter Block Diagram

6. ROM • 6 words x 8-bits • Coefficient determined by Control Unit by way ofdecoder

7. Control Unit • INPUTS: Restart FailSafe NewInput; • OUTPUTS: S1 S2 S3 C0 C1 C2 Shift LoadI LoadC LoadMul LoadX LoadSum LoadFinal Clr1 Clr2

8. State Machine IDLE Clear registers Load RAM with zeros GOTSIGNAL Load signal S2=0 SHIFT 3 times (d,1) (0,d) WAIT Select coeff α3 (1,d) MUL LoadI=1 LoadC=1 BYPASS S3=1 LoadI=1 Shift Select next coeff FINAL LoadFinal=1 ADD LoadMul=1 LoadX=1 STORE LoadX=1 Clr1=1 X 4 SUM LoadSum=1

9. 16-bit Carry Ripple Adder • Composed of four 4-bit carry ripple adders • Two 16-bit inputs and one 16-bit output

10. Multiplier • 8 bit x 8 bit • 16 bit output

11. Multiplier

12. FIFO • 8 elements deep • 8 bits wide

13. Output => α3*x0 + α2*x1 + α1*x2 + α0*x3 + x4 shift1 shift2 shift3 shift4 shift5 shift6 shift7 * α3 * α2 * α1 * α0 * 1

14. Outputs • T0 => x0 • T1 => α0*x0+ x1 • T2 => α1*x0+ α0*x1+ x2 • T3 => α2*x0+ α1*x1+ α0*x2 + x3 • T3 => α3*x0+ α2*x1+ α1*x2 + α0*x3 + x4 • Tn => α3*xn-3+ α2*xn-2+ α1*xn-1 + xn