Orsay’s proposition for the L2  trigger system

1. March the 13th, 2001 Orsay’s proposition for the L2 trigger system • detailed description of the architecture • distribution of the work • costs • schedule • firmware Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot

2. Trigger Crate L2 trigger mosaic of boards CPU board Processor : Pentium III 850 MHz Dimensions : 6U Make : VMIC Type : VMIVME-7740 VME bus PCI bus 33 MHz, 32 bits Trigger adaptation board Function : interface between the trigger crate and the processor board Magic bus 128 data bits 32 add bits 20 MHz ECL signals

3. Dimensions 400 mm 160 mm 6U board 233 mm 366 mm 9U board

4. Geometry of the boards 9U board 6U board Hard drive mezzanine board The proportions of the boards are respected

5. Geometry of the boards (profile view) 9U components side (a few thin (height : 1.20 mm) TTL drivers will be on the other side) 6U components side mezzanine components side PCI interface TTL drivers Hard drive 9U board 6U board 9U board The proportions of the boards are respected ~12mm

6. Electronics functions 9U board 6U board VME mezzanine board Hard drive VME 33 MHz PCI PCI / Add-on interface 20 MHz 33 MHz EIDE Add-on Magic bus Display drivers : electrical isolation FPGA electrical conversion to ECL FIFOs : DMA storing Add-on / Magic bus interface & PCI / Magic bus arbitration The proportions of the boards are respected

7. Electronics placement 9U board 6U board VME TTL driver mezzanine board Hard drive VME TTL driver PCI AMCC S5935 PQFP 160 TTL drivers Control signals Add-on EIDE ECL drivers Magic bus Display clk40MHz EPROM Altera APEX 20K200 Fineline BGA 484 FIFOs The proportions of the boards are respected

8. FPGA • pin limited • wide logics capacity (8320 cells, 13 kB mem) • high rate • low voltage • BGA package • unique FPGA flexibility • inputs-outputs known beforehand

9. FPGA details Control signals from J1 and J2 connectors Add-on bus 60 20 4 Altera APEX 20K200 Fineline BGA 484 Switches 1 Clock 5 TTL drivers control signals Total : 366 signals out of 376 available 5 Display 23.2 mm 195 Magic bus 5 EPROM 32 +5 FIFOs output data and control signals ECL drivers data and control signals 32+ 2 when unclear, the given count is approximative by excess 23.2 mm height : 1.86 mm the geomtry of the input/output pins is not respected

11. 9U board from the factory The proportions of the boards are respected

12. most components are assembled TTL driver TTL driver TTL drivers EIDE ECL drivers Add-on Magic bus clk40MHz EPROM Altera APEX 20K200 Fineline BGA 484 FIFOs The proportions of the boards are respected

13. the inside cut is sawed, the VME connectors are soldered TTL driver TTL driver TTL drivers EIDE ECL drivers Add-on Magic bus clk40MHz EPROM Altera APEX 20K200 Fineline BGA 484 FIFOs The proportions of the boards are respected

14. the front pannel and support bars are screwed TTL driver TTL driver TTL drivers EIDE ECL drivers Add-on Magic bus clk40MHz EPROM Altera APEX 20K200 Fineline BGA 484 FIFOs The proportions of the boards are respected

15. the mezzanine board is relatively simple EPROM PCI AMCC S5935 PQFP 160 add-on If all signals don’t pass through 2 PMC connectors, the board is enlarged to receive a 3rd one

16. Grounding of the boards 9U board 6U board backplane mezzanine board The proportions of the boards are respected

17. PCBs and hardware to design • a 9U board • a mezzanine board • the 9U front panel • the aluminium support bars • no modification on the 6U board

18. Manpower at Orsay • schematics, firmware : • Bernard Lavigne, Philippe Cros (+ a technician if necessary) • tests : • Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot • PCB design : • board design group • front panel, support bars, mechanics questions : • mechanics group • production, assembly : • private companies

19. Costs (US $) prototype (3) production (30) PCB 1700 1100 9U Components 900 500 Assembly 400 200 PCB 250 150 mezzanine Components 100 50 Assembly 0 0 assembled at Orsay 3350 Total 2000 Whole budget : $ 70000 nota : The front panel and mechanics components are taken in account in the components budget The costs don’t count the CPU board, neither the engineering cost which is around $20000

20. Schedule for the prototype march april may june july august september schematics assembly PCB design production 9U front panel / bars schematics assembly mezzanine PCB design production tests firmware l2 system software

21. Firmware • composed of blocks : necessity of a documentation • with input-outputs-functionality of each block • distribution of the blocks : • Maryland : Magic bus, PIO, TSI, DMA • Orsay : Add-on, DMA ? • common language : Verilog, AHDL, VHDL ? • most complex part of the project, • the development should start soon

22. FPGA blocks Altera APEX 20K200 Fineline BGA 484 Add-on bus Other Add-on bus interface TSI ECL signals Switches ECL drivers data and control signals Clock Display EPROM local bus PIO TTL drivers control signals DMA MB interface control signals from P1/P2 connectors Magic bus FIFOs output data and control signals the geomtry of the input/output pins is not respected

23. Conclusion : • The solution we propose : • cheap • realistic schedule • manpower and experience • technically reliable • flexible • developments equally shared