csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces

csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces Chuck Benz Chuck Benz ASIC & FPGA Design http://asics.chuckbenz.com

Outline • Describe processor interfaces and CSRs • Discuss automating CSRs • Example using csrGen – template file and result • More complete list of csrGen features • Future directions

0 Field1 bitA bitB bitC bitD 1 Field2 2 bitX1 bitX2 bitX3 bitX4 bitX5 bitX6 3 More 4 And more Example CSR memory map • And so forth…

read write data data read write and mux address decode CS_L WR_L Interface logic Address Example CSR logic

CSR verilog code fragments • output [7:0] field2 ; • reg [7:0] field2, field2_D ; • always @ (*) begin field2_D = field2 ; if (write) case (address) 1: field2_D = up_datain[7:0] ; endcase case (address) 1: up_dataout_D[7:0] = field2 ; endcase • always @ (posedge clock or negedge resetl) if ( ! resetl) field2 <= 0 ; else field2 <= field2_D ;

Why Automate? • Time savings • Correctness • Consistency, shared structures • Generate more than RTL code

Ways to Automate CSRs (1) • Code fragments vs. complete RTL • create the fragments, maybe use `ifdef, OR • blend automated stuff with the rest of the Verilog code • Results: • verilog (or VHDL?) RTL code • defines for verification, software code • declarations/instantiation for hierarchy • documentation (format?)

Ways to Automate CSRs (2) • What types of CSRs ? • R/W • RO • sticky (COR/W1C) • counters (COR/W1C) • pulse • Single or many modules • Input format ?

csrGen example template part 1 %I read %I write %I address 4 %I up_datain 8 %OF up_dataout 8 %A 0 7:0 field1 %A 1 7:0 version RO %A 2 3:0 field2 6 someerror sticky W1C

csrGen example template part 2 %VCL if (write) case (address) %writecase endcase if (read) case (address) %readcase endcase %E %AUTO

csrGen example resultpart 1 module chip_up_ifc (/*AUTOARG*/) ; input clock, initl ; input [7:0] version; input someerror; input read; input write; input [3:0] address; input [7:0] up_datain; output [7:0] field1; output [3:0] field2; output [7:0] up_dataout; reg [7:0] field1, field1_D; reg [3:0] field2, field2_D; reg someerrorS, someerrorS_D; reg [7:0] up_dataout, up_dataout_D ;

csrGen example resultpart 2 always @ (/*AUTOSENSE*/) begin field1_D = field1 ; field2_D = field2 ; someerrorS_D = someerrorS | someerror ; up_dataout_D = up_dataout ;

csrGen example resultpart 3 Continuing the always block: if (write) case (address) 0: begin field1_D = up_datain[7:0] ; end 1: begin end 2: begin field2_D = up_datain[3:0] ; someerrorS_D = (someerrorS_D & ~up_datain[6]) | someerror ; end endcase

csrGen example resultpart 4 Finishing the always block: if (read) case (address) 0: begin up_dataout_D[7:0] = field1 ; end 1: begin up_dataout_D[7:0] = version ; end 2: begin up_dataout_D[3:0] = field2 ; up_dataout_D[6] = someerrorS ; end endcase end

csrGen example resultpart 5 always @ (posedge clock or negedge initl) if ( ! initl) begin field1 <= 0 ; field2 <= 0 ; someerror <= 0 ; up_dataout <= 0 ; end else begin field1 <= field1_D ; field2 <= field2_D ; someerrorS <= someerrorS_D ; up_dataout <= up_dataout_D ; end endmodule

Beyond simple Example is just basic, csrGen has many more features • various CSR structures (more later) • An address definition can be repeated • incrementing index appended to field names • or for single bits, constructing a vector spanning addresses • %VCL and %V have simple repeat structure • the missing verilog Generate statement • simply unrolls a print statement ▪▪▪► any structure

More features • Verilog tasks can be called for write or read to address • Wide fields can be broken across several addresses • Read multiplexer can be pipelined • Reset value of flops can be set • Direct value for flops bypasses _D structure

Supported CSR properties • internal to module (no IO declarations for CSR field) • read only • write only • sticky • clear-on-read • write-1-to-clear • counters • pulses (see paper on CD for full feature list, details)

Verification • Automated definitions: • define csr_address_name 42 • define csr_width_name 8 • define csr_range_name 7:0 • Allows for automated testing • R/W • reset values • clear on read, write-1-to-clear tests

Futures, Enhancements • Open source tool, change as desired • More CSR structures (send requests, enhancements) • Generate HTML table for each address • Parser and data structures could be better

Lessons, Ideas • More than a tool • a concept of how design work can evolve • “Spec driven design” • but small step rather than giant leap • focused on one area of a design • emphasis on integrating • Other ways to do this • template file could be generated from other tool • emacs mode auto expansion from comments (pragmas) • object oriented design language ?

Conclusion • Avoid tedious, error prone work • Here's a tool for your tool box • feedback is welcome csrGen.pl http://asics.chuckbenz.com cbenz@chuckbenz.com

csrGen: Automated CSRs for ASIC/FPGA Processor Interfaces