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ENG2410 Digital Design

ENG2410 Digital Design. LAB #6 Sequential Logic Design (Flip Flops). Lab Objectives. Understand the concept of sequential circuit. Understand sequential circuit design flow. Design a simple D Flip Flop using VHDL. Part 1 D Flip Flop. Design D-FF with asynchronous reset logic using VHDL.

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ENG2410 Digital Design

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  1. ENG2410 Digital Design LAB #6 Sequential Logic Design (Flip Flops)

  2. Lab Objectives • Understand the concept of sequential circuit. • Understand sequential circuit design flow. • Design a simple D Flip Flop using VHDL. ENG241/Lab #6

  3. Part 1D Flip Flop • Design D-FF with asynchronous reset logic using VHDL. • Use an LED to display the output of the FF. ENG241/Lab #6

  4. Sample Sequential CircuitPositive Edge-Triggered D Flip-Flop • Note that this FF does not have a “reset” input ENG241/Lab #6

  5. Academic Misconduct • Reports and demos are submitted as a group, but it is a SINGLE group effort • You may talk with other groups but sharing codes or reports is NOT ALLOWED • Copying reports from previous years is also NOT ALLOWED • If we find copying we are REQUIRED to report it

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