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Chapter 8 Computer Arithmetic

Chapter 8 Computer Arithmetic. 8.1 Unsigned Notation. Non-negative notation It treats every number as either zero or a positive value Range: 0 to 2 n -1 Unsigned Two ’ s Complement

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Chapter 8 Computer Arithmetic

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  1. Chapter 8 Computer Arithmetic

  2. 8.1 Unsigned Notation • Non-negative notation • It treats every number as either zero or a positive value • Range: 0 to 2n-1 • Unsigned Two’s Complement • Negative numbers have a 1 as the most significant bit and positive number (or zero) have 0 as the leading bit. • Range: -2n-1-1 to 2n-1-1 • Refer to Table 8.1

  3. 8.1 Unsigned Notation(continued) • Addition and Subtraction(Figure 8.1)

  4. Figure 8.1

  5. 8.1 Unsigned Notation(continued) • Arithmetic overflow in addition • In non-negative notation, carry bit can set an overflow flag. • In two’s complement notation an overflow can occur at either end of the numeric range. (Figure 8.2)

  6. Figure 8.2

  7. 8.1 Unsigned Notation(continued) • Arithmetic overflow in subtraction • X-Y is implemented as X+(-Y) • Y is converted to -Y by taking it’s two’s complement. • Implementation of micro-operation SUB: XX-Y (Figure 8.3)

  8. Figure 8.3

  9. 8.1 Unsigned Notation(continued) • Overflow generation in unsigned two’s complement subtraction (Fig. 8.4) • The result should be larger than or equal to zero.

  10. Figure 8.4

  11. 8.1 Unsigned Notation(continued) • Multiplication • A simple algorithm for xy Z =0 For I=1 to y do { z = z+x } • Shift-add multiplication • Partial products

  12. 8.1 Unsigned Notation(continued) • Multiplication • another simple algorithm for xy • The result in two n-bits registers, V.U U =0 For I = 1 to n do { IF Y0= 1 then CU = U +X; linear shift right CUV; circular shift right Y } • Refer to table 8.2 • RTL code for realize the algorithm • Refer to Table 8.3 • Hardware implementation (Refer to Figure 8.5)

  13. Figure 8.5

  14. 8.1 Unsigned Notation(continued) • Multiplication • Booth’s algorithm (Figure 8.6) • This algorithm works directly on two’s complete numbers. • UV X*Y U =0; Y-1 = 0; For I=1 To n DO {IF start of a string of 1’s in Y THEN U = U-X; IF end of a string of 1’s in Y THEN U =U+X; Arithmetic shift right UV; Circular shift right Y AND copy Y0 to Y-1}

  15. Figure 8.6

  16. Division • Z = X  Y • Z = 0; WHILE x  y DO { z = z + 1, x = x-y }

  17. Division(continued) • Shift-subtract division of two binary values. • Dividend: UV, divisor: X, quotient: Y, remainder: U • IF U  X THEN exit with overflow; Y = 0; C = 0; FOR i = 1 TO n DO { linear shift left CUV; linear shift left Y; IF CU  X THEN {Y0 = 1, U = CU -X } }

  18. Division(continued) • Non-restoring division algorithm • Re-storing division algorithm

  19. Figure 8.7

  20. How to compare U and X • Figure 8.8

  21. Figure 8.8

  22. Figure 8.9 Hardware implementation of restoring algorithm

  23. 8.2 Signed Notations • Signed-magnitude • Signed-two’s complement • To add and subtract two signed-two’s complementation values, we simply treat the sign bit as the most significant bit of magnitude. • Multiplication can be accomplished by using Booth’s algorithm

  24. 8.3 Binary Coded Decimal • BCD Format: 4 bits can represent one decimal digit. • Addition and subtraction (Figure 8.13) • We adjust the hardware that adds numbers to account for the BCD representation. • When the sum of two digits is more than 9, adding 6 to the result generated by a binary adders produces the correct result.(Figure 8.11) • Nine’s complement (Figure 8.12) or ten’s complement can be used for subtraction.

  25. Figure 8.11

  26. Figure 8.12

  27. Figure 8.13

  28. 8.4 Special Arithmetic Hardware • Pipelining • Arithmetic pipeline (Figure 8.14) • To increase the throughput, the numbers of results generated per time unit. • Speed up: a metric used to measure the performance of a pipeline.

  29. 8.4 Special Arithmetic Hardware(continued) • Pipelining The maximum speedup • Lookup table (Figure 8.15 and 8.16)

  30. Figure 8.14

  31. Figure 8.15

  32. Figure 8.16

  33. 8.4 Special Arithmetic Hardware(continued) • Carry-save adder(Figure 8.17) • Wallice Tree: a combinatorial circuit used to multiply two numbers.(Figure 8.18)

  34. Figure 8.17

  35. Figure 8.18

  36. Example X * Y X = 111 Y = 110 ----- 000  PP0 111  PP1 111  PP2 ------- 101010  Final sum calculated

  37. Figure 8.19

  38. Example X * Y (6-bit) X = 1011 Y = 1110

  39. Figure 8.20

  40. Figure 8.21 An 8X8 Wallice Tree Multiplier

  41. 8.5 Floating Point Numbers • Number format • Normalized • NoN Not a number • Biasing • Numeric characteristic • Precision • Gap • Range • Rounding • Guard bit

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