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Lecture 26: TPU Programming

Lecture 26: TPU Programming. Computer Engineering 211 Spring 2002. Ref-time 1. offset. Ref_Time = Ref-time 1 + offset. The pin state is not forced into an immediate output. Another TPU Function: Output Compare (OC). Program as an output channel. Ability to generate an event on the output.

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Lecture 26: TPU Programming

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  1. Lecture 26: TPU Programming Computer Engineering 211 Spring 2002

  2. Ref-time 1 offset Ref_Time = Ref-time 1 + offset The pin state is not forced into an immediate output. Another TPU Function: Output Compare (OC) Program as an output channel. Ability to generate an event on the output. A single output transition, a single pulse, or a continuous 50% duty cycle pulse train.

  3. Ref-time 1 offset Ref_Time = Ref-time 1 + offset Pin state forced to high (immediate output selected). Output Compare (OC) Contd. OC parameters specified by the CPU program: Ref-time 1 as a pointer into the parameter space of any of the 16 channels. Parameter address space: 0x3041 00 – 0x3041 fe Need to specify only 8-bits of address for REF_ADDR1. OFFSET: a 16-bit quantity: 0x0 – 0x8000.

  4. (REF_ADDR1) OFFSET REF_TIME = (REF_ADDR1) + OFFSET Output Compare Contd. OC initialization (host service request of 01 -- host initiated pulse mode) writes the current value: TCR1  0x3041 ec; TCR2  0x3041ee Program channel 0 for this pulse.

  5. 7:10 11:13 14:15 0:6 TBS PAC PSC Time Base Selection 01xx: output channel 0100: capture TCR1, match TCR1 0101: capture TCR1, match TCR2 0110: capture TCR2, match TCR1 0111: capture TCR2, match TCR2 1xxx: do not change TBS Pin State Control 11:do not force any state input pin 01: force high 10: force low Pin Action Control 000:do not change pin state on match 001: high on match 010: low on match 011: toggle on match 1xx: do not change PAC OC Channel Control Options

  6. Do not force initial state Capture TCR1, match TCR1 0100 011 11 (REF_ADDR1) Toggle on match OFFSET REF_TIME = (REF_ADDR1) + OFFSET OC Channel control contd.

  7. (REF_ADDR1) OFFSET REF_TIME = (REF_ADDR1) + OFFSET Force high Capture TCR1, match TCR1 0100 010 01 Low on match OC Channel control contd.

  8. Channel W Channel Control (9 bits) 0x3041W0 OFFSET 0x3041W2 0x3041W4 RATIO REF_ADDR1 0 REF_ADDR2 0 REF_ADDR3 0 0x3041W6 REF_TIME 0x3041W8 ACTUAL_MATCH_TIME 0x3041Wa Other OC Parameters We will write 0’s into RATIO, REF_ADDR2, and REF_ADDR3.

  9. OC Output Parameters When a channel is initialized for OC through a service request of 01, REF_TIME is computed as (REF_ADDR1) + OFFSET and placed in parameter REF_TIME. REF_TIME is the next time instant when an event would occur (and an interrupt is raised). (this is the match event: compare TCR1/2 with REF_TIME for a match). ACTUAL_MATCH_TIME is updated with the TCR1/2 time when the match is serviced (by raising an interrupt, and changing the level of the output channel).

  10. (REF_ADDR1) OFFSET REF_TIME = (REF_ADDR1) + OFFSET OC Programming Point REF_ADDR1 to 0x3041 ec (TCR1 value captured at this parameter address). OFFSET = 0x1000 with TCR1 resolution at 1 micro-s: 4.096 milli-s. Channel function code for OC: 0x4 CFSR[ch]  0x4

  11. OC Programming contd. Channel Sequence: 0x: all code for OC is executed 1x: only 0xec & 0xee are initialized with TCR1, TCR2 followed by an interrupt. HSQR[ch]  00 Channel Service Request: 00: reset (service complete indicated by TPU) 01: host initiated pulse mode HSRR[ch]  01

  12. OC Channel Initialization lis r5, 0x30 //base addr of TPU memory space // disable channel 0 lhz r6, 0x401e(r5) // load CPR1 andi r6, r6, 0xfffc // 0 into LSB 2 bits sh r6, 0x401e(r5) // channel control li r6, 0x8f //01000 1111 sh r6, 0x4100(r5) //OFFSET li r6, 0x1000 sh r6, 0x4102(r5) // RATIO and REF_ADDR1 li r6, 0x00ec //RATIO=0, REF_ADDR1:TCR1 sh r6, 0x4104(r5)

  13. OC Channel Initialization contd. // REF_ADDR2 & REF_ADDR3 li r6, 0x0 sh r6, 0x4106(r5) // Host sequence lhz r6, 0x4016(r5) andi r6, r6, 0xfffc sh r6, 0x4016(r5) // host service request li r6, 0x1 sh r6, 0x401a(r5) // enable the channel : priority 11 lhz r6, 0x401e(r5) // load CPR1 andi r6, r6, 0xffff // 11 into LSB 2 bits sh r6, 0x401e(r5)

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