LOLA 1553 Chip Overview

1. LOLA 1553 Chip Overview Rod Barto NASA Office of Logic Design 5/7/2006

2. One Chip 1553 Solution Sital 1553 Core User RAM Backend interface DMA Interface 1553 Transformer SAM, WC Discrete digital outputs User system data Discrete digital inputs 1553 Transformer controls Event counters Actel RTAX2000S FPGA LOLA 1553 Chip Overview

3. Chip Function Overview • Internal Interfaces • Discrete digital outputs • Discrete digital inputs • DMA interface • Event counters • External device interface • Internal status and monitoring • Command buffer • Internal event counters • Error conditions • Status register • Reset conditions LOLA 1553 Chip Overview

4. Discrete Digital Outputs • 16 bit output • All set to 0 (low) on reset • Bits cannot be individually set • Bits can be read back at pins • Bit transitions are synchronous to clock LOLA 1553 Chip Overview

5. Discrete Inputs • 16 bit input • All read simultaneously • Synchronized to 20 MHz clock • Sampled every clock cycle LOLA 1553 Chip Overview

6. DMA and External Devices LOLA 1553 Chip Overview

7. DMA Operation • Addressing • 24 bit auto-incrementing register that can be read and written • Address word is read back at pin outputs • Address drivers are always enabled • Data input and output busses are separate LOLA 1553 Chip Overview

8. External Device Operation • External devices are those that are added by the user outside the 1553 chip • Operation is the same as for DMA, except that addressing is by sub-address and word number • Read and write timing is same as DMA • Use same data busses as DMA LOLA 1553 Chip Overview

9. External Event Counters • 16-bit rising edge triggered ripple counters • Saturate at 2^16-1 events • 4 counters provided • All 4 counters read out by single 1553 read • All 4 counters reset by single 1553 write LOLA 1553 Chip Overview

10. Internal event counters • Same as external event counters, but do not saturate • 4 counters provided, currently count • New_command (occurs at start of every command received), • Meok (message ended OK) LOLA 1553 Chip Overview

11. Command buffer • Stores last 32 commands • Reads out most recent command first • Resets only on core reset LOLA 1553 Chip Overview

12. Status Register • 16 bit register holding error flags • Upper 8 bits = 0 • Setting a bit in the register sets the terminal flag • Setting the terminal flag causes an interface reset • Register resets to 0000h when read LOLA 1553 Chip Overview

13. Status Register Bits LOLA 1553 Chip Overview

14. Sub-address Summary LOLA 1553 Chip Overview

15. Usage Statistics Compile report: =============== Family : Axcelerator Device : AX500 Package : 208 PQFP Post-Combiner device utilization: SEQUENTIAL (R-cells) Used: 2232 Total: 2688 (83.04%) COMB (C-cells) Used: 2633 Total: 5376 (48.98%) LOGIC (R+C cells) Used: 4865 Total: 8064 (60.33%) RAM/FIFO Used: 2 Total: 16 * test version only IO w/Clocks Used: 51 Total: 115 CLOCK (Routed) Used: 4 Total: 4 HCLOCK (Hardwired) Used: 1 Total: 4 PLL Used: 0 Total: 8 * Stats for test version of chip. Actual usage will be less. LOLA 1553 Chip Overview