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Practical Universal Computers

Practical Universal Computers. Bits Wires Gates Turing Machines. Prof. Bienvenido Velez. Lecture 4. Outline. The von Neumann Architecture Big Ideas: Interpretation Stored program concept Designing a simple processor Instruction Set Architecture Data Paths Control Unit.

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Practical Universal Computers

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  1. Practical Universal Computers Bits Wires Gates Turing Machines Prof. Bienvenido Velez Lecture 4 INEL 4206 Microprocessors Lecture 4

  2. Outline • The von Neumann Architecture • Big Ideas: • Interpretation • Stored program concept • Designing a simple processor • Instruction Set Architecture • Data Paths • Control Unit INEL 4206 Microprocessors Lecture 4

  3. The (John) Von Neumann Architecture(late 40’s) Allow communication with outside world I/O devices Central Processing Unit (CPU) Interprets instructions Stores both programs and data Memory After 60 years … most processors still look like this! INEL 4206 Microprocessors Lecture 4

  4. Interconnected registers, muxes, decoders, … The von Neumann ArchitectureCentral Processing (CPU) I/O devices Control Unit (FSM) Central Processing Unit (CPU) active control status Data Paths Memory passive INEL 4206 Microprocessors Lecture 4

  5. Easy IData Paths A bus PC A0 A D D R E S S B U S D A T A B U S DI A B ALU AC Typically, designing a processor is an iterative (aka trial end error) process INEL 4206 Microprocessors Lecture 4

  6. The (John) Von Neumann ArchitectureThe Memory Unit word size I/O devices address space Central Processing Unit (CPU) Memory INEL 4206 Microprocessors Lecture 4

  7. The (John) Von Neuman ArchitectureStored Program Concept Program Instructions Program Data • Programs and their data coexist in memory • Processor, under program control, keeps track of what needs to be interpreted as instructions and what as data. INEL 4206 Microprocessors Lecture 4

  8. DefinitionInstruction Set Architecture • What it is: • The programmers view of the processor • Visible registers, instruction set, execution model, memory model, I/O model • What it is not: • How the processors if build • The processors internal structure INEL 4206 Microprocessors Lecture 4

  9. 15 14 10 9 0 I opcode X Easy IA Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Format (16 bits) I = Indirect bit INEL 4206 Microprocessors Lecture 4

  10. Easy IA Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Set Easy all right … but universal it is! INEL 4206 Microprocessors Lecture 4

  11. Easy IMemory Model 8 bits 8 bits INEL 4206 Microprocessors Lecture 4

  12. Easy IA Simple Accumulator Processor Instruction Set Architecture (ISA) • Accumulator (AC) is implicit operand to many instructions. No need to use instruction bits to specify one of the operands. More bits left for address and opcodes. • Although simple, Easy I is universal. (given enough memory). Can you see this? • Immediate bit specifies level of indirection for the location of the operand. I = 0: operand in X field (immediate). I=1 operand in memory location X (indirect). Some Immediate Observations on the Easy I ISA INEL 4206 Microprocessors Lecture 4

  13. Programming the Easy I • Compute the sum of the even numbers between 1 and N [Blackboard] INEL 4206 Microprocessors Lecture 4

  14. Programming the Easy I • Compute the sum of the even numbers between 1 and N High Level Language Version int suma = 0; Int count = 0; For (count=2; count <= N; count += 2) { suma += count; } INEL 4206 Microprocessors Lecture 4

  15. Programming the Easy I • Compute the sum of the even numbers between 1 and N Easy I Memory Program Easy I Assembly Language Version Data 512 suma count 514 INEL 4206 Microprocessors Lecture 4

  16. Compute the sum of even numbers from 2 to N Easy I Assembly Language & Machine Code Versions dddddddddd = Don’t Care INEL 4206 Microprocessors Lecture 4

  17. Easy IData Paths A bus PC A0 A D D R E S S B U S D A T A B U S DI A B ALU AC Typically, designing a processor is an iterative (aka trial end error) process INEL 4206 Microprocessors Lecture 4

  18. Processor Design Process Start Initial Data Path Design c-unit Measure Happy? yes Done no Review Data Path INEL 4206 Microprocessors Lecture 4

  19. Memory Bus Easy IMemory Interface MEMORY CPU address data word memory op {R,W,NOP} INEL 4206 Microprocessors Lecture 4

  20. Easy IControl Unit(Level 0 Flowcharts) Fetch Read next instruction Decode FetchOp Determine what it does and prepare to do it. Fetch operands. Execute Do it! We will ignore indirect bit (assuming I = 0) for now INEL 4206 Microprocessors Lecture 4

  21. Easy IControl Unit(Level 1 Flowcharts) Reset Fetch Fetch Op Aopr Sopr Load Store BrN Jump What? Level 1: Each box may take several CPU cycles to execute INEL 4206 Microprocessors Lecture 4

  22. What makes a CPU cycle? CU Logic FSM logic state Data Paths Logic ALU, latches, memory Cycle time must accommodate signal propagation INEL 4206 Microprocessors Lecture 4

  23. Easy I – Timing ExampleALU Operation le DI A B op ALU AC le INEL 4206 Microprocessors Lecture 4

  24. Easy I – Timing ExampleMemory Operation le DI A B op ALU AC le INEL 4206 Microprocessors Lecture 4

  25. Key Performance Metric Performance Assessment IE ~ Instructions executed CPI ~ Clock cycles per instruction CT ~ Cycle time Execution time = IE  CPI  CT INEL 4206 Microprocessors Lecture 4

  26. RESET Easy IControl Unit(Level 2 Flowcharts) reset1 Easy I Byte Addressable Can you tell why? reset2 Invariant At the beginning of the fetch cycle AO holds address of instruction to be fetched and PC points to following instruction fetch Each box may take only one CPU cycle to execute INEL 4206 Microprocessors Lecture 4

  27. aopr sopr load store brn jump FETCH Easy IControl Unit(Level 3 Flowcharts) fetch Memory Bus Operation Invariant At the beginning of the fetch cycle AO holds address of instruction to be fetched and PC points to following instruction (I=0) (I=1) fetchop 00 11x 00 00x 00 101 00 100 00 010 00 011 opcode Opcode must be an input to CU’s sequential circuit INEL 4206 Microprocessors Lecture 4

  28. AOpr Easy IControl Unit(Level 2 Flowcharts) aopr Restore fetch invariant fetch INEL 4206 Microprocessors Lecture 4

  29. SOpr Easy IControl Unit(Level 2 Flowcharts) sopr fetch INEL 4206 Microprocessors Lecture 4

  30. Load Easy IControl Unit(Level 2 Flowcharts) load1 load2 load3 fetch INEL 4206 Microprocessors Lecture 4

  31. Store Easy IControl Unit(Level 2 Flowcharts) store1 store2 fetch INEL 4206 Microprocessors Lecture 4

  32. BrN Easy IControl Unit(Level 2 Flowcharts) brn1 Assume branch not taken. Allow AC:15 to propagate. AC:15 1 (AC<0) 0 (AC>0) brn2 fetch Can we accomplish all this in 1 cycle? How? Bit 15 of AC input to the CU’s sequential circuit INEL 4206 Microprocessors Lecture 4

  33. Inside the Easy-I PC ABUS PC pcis 1 0 0 +2 Adder PC capable of loading and incrementing simultaneously 00 01 10 11 pcsel PC INEL 4206 Microprocessors Lecture 4

  34. JUMP Easy IControl Unit(Level 2 Flowcharts) jump fetch INEL 4206 Microprocessors Lecture 4

  35. Easy IData Paths (with control points) A bus is A D D R E S S B U S PC D A T A B U S sel sel 1 0 le DI A0 le A B op ALU AC le sel 0 1 INEL 4206 Microprocessors Lecture 4

  36. Easy I - Control Unit Control Unit EDBsel AC:15 AOle AOsel OpCode ACle DIle PCis I bit PCsel MEMop Current State ALUop Next State DataPaths + state 11 17 clock INEL 4206 Microprocessors Lecture 4

  37. Easy IControl Unit State Transition Table (Part I) INEL 4206 Microprocessors Lecture 4

  38. Easy IControl Unit State Transition Table (Part II) CU with 14 states => 4 bits of state INEL 4206 Microprocessors Lecture 4

  39. Easy-I Control Unit – Some missing details 4-bit Encodings for States ALU Operation Table We know how to implement this ALU ! Control Bus Operation Table INEL 4206 Microprocessors Lecture 4

  40. Easy IControl Unit State Transition Table (Part I) INEL 4206 Microprocessors Lecture 4

  41. Easy IControl Unit State Transition Table (Part II) INEL 4206 Microprocessors Lecture 4

  42. aopr sopr load store brn jump FetchOp Easy IControl Unit(Level 3 Flowcharts) Memory Bus Operation fetchop 00 11x 00 00x 00 101 00 100 00 010 00 011 opcode Opcode must be an input to CU’s sequential circuit INEL 4206 Microprocessors Lecture 4

  43. Building the Easy-I C-Unit2 Approaches • Harwired • Apply well known sequential circuit techniques • Micro-programmed • Treat state transition table as a program • Build a new abstraction layer A program The Microprogramming abstraction level INEL 4206 Microprocessors Lecture 4

  44. Building the Easy-I C-UnitHardwired Approach Control Unit ROM control point signals next state 10 Memory Unit 2 control bus 11 state address bus data bus 4 Data Paths AC:15 5 DI<10:14> INEL 4206 Microprocessors Lecture 4

  45. 64 ROM Addresses with identical content Easy IControl Unit State Transition Table (Part II) 11-bit ROM address 17-bit ROM outputs INEL 4206 Microprocessors Lecture 4

  46. Programmable Logic Arrays INEL 4206 Microprocessors Lecture 4

  47. INEL 4206 Microprocessors Lecture 4

  48. Building the Easy-I C-Unit2 Approaches • Harwired • Apply well known sequential circuit techniques • Micro-programmed • Treat state transition table as a program • Build a new abstraction layer A program The Microprogramming abstraction level INEL 4206 Microprocessors Lecture 4

  49. PC Building the Easy-I C-UnitMicro-programmed Approach 4 Program (Comb Logic) 00 01 10 11 unused Opcode Mapping 0 1 fetch brn2 AC:15 2 opcode DataPath Control INEL 4206 Microprocessors Lecture 4

  50. Finding the first execute stateCombinational Logic Opcode Mapping opcode INEL 4206 Microprocessors Lecture 4

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