Wang-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang Department of Electrical Engineering, NTU ICCAD 2007

1. An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning Wang-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang Department of Electrical Engineering, NTU ICCAD 2007

2. Outline • Introduction • Problem Formulation • Algorithm • Experimental Results • Conclusions

3. MSV Design • Multiple-Supply-Voltage design is effective for dynamic power reduction • dynamic power = 0.5·k·f·C·Vdd2 • Trade timing slacks for power reduction under timing requirements

4. MSV in Physical Design • At floorplanning stage • Voltage Island-Driven Floorplanning [Ma et al., ICCAD-07] • At post-floorplanning stage • Voltage Island Generation under Performance Requirement for SoC Designs [Mak and Chen, ASPDAC-07] • At placement stage • At post-placement stage

5. Problem Formulation • Inputs • A set of blocks; each block has a coordinate, a set of available supply voltage, and a set of corresponding power and delay • A netlist • A timing constraint • Objectives • Assign voltage for each block such that • Timing constraint is satisfied • Total power consumption is minimized • Total power-network routing resource is minimized

6. Power Network Routing Resource • Voltage Island • Blocks are adjacent and operate at the same voltage • Power Network Routing Resource (PNRR) • The half-perimeter wirelength (HPWL) of a voltage island b6 b3 b5 b7 b2 b1 b4

7. ILP Overview Minimize: Subject to: blocks’ power blocks’ power level shifters’ power level shifters’ power voltage islands minimization voltage islands minimization PNRR consideration PNRR consideration timing constraints

8. Power Minimization • Minimize total power consumption • Blocks: n blocks; m available supply voltages Minimize: Subject to: power consumption when bi is at Vddj 0: bi is not at Vddj 1: bi is at Vddj

9. Power Minimization (cont.) • Minimize total power consumption • Level shifters are necessary for a net from low- to high- voltage bi is at Vddk; bj is at Vddl 0: Vddk is not lower than Vddl 1: Vddk is lower than Vddl Minimize: Subject to: power consumption of the level shifter from Vddk to Vddl

10. Block-Adjacency Data Structures • Grid-based Graph has quadratic nodes • Block-adjacency Graph (BAG) • has linear nodes • is fast to determine adjacent nodes y y b6 b3 b5 b7 b2 b1 x b4 x n6 n3 n5 n7 n1 n2 n4

11. Voltage Islands Minimization • Minimize total color differences in the BAG n6 n5 n3 n7 n1 n2 n4 Minimize: Subject to:

12. PNRR Minimization • Minimize total power-network routing resource • Power Network Routing Resource (PNRR) • The half-perimeter wirelength (HPWL) of a voltage island Minimize: Subject to: resource = 18 resource = 12 resource = 20 HPWL of the bounding box enclosing bs and bt

13. Wire Delay Formulation • Positions of level shifters effect wirelength and wire delay • Box-growing wirelength estimation LS LS wire delay = 12 wire delay = 18 wire delay = 12 white space = 3 white space = 5 probability = white space / total white space probability= 0.3 probability= 0.5 wire delay= 6 wire delay= 10

14. Experimental Results • Setting A doesn’t consider PNRR; Setting B does • Reduce the PNRR by up to 19%

15. Conclusions • They proposed a graph-based representation BAG to capture blocks’ adjacencies • The ILP algorithm consists of • Level shifter’s positions predication • Voltage-island-clustering equations • Power-network routing-resource equations