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William Stallings Computer Organization and Architecture 7th Edition

William Stallings Computer Organization and Architecture 7th Edition. Chapter 5 Internal Memory. Semiconductor Memory Types. Semiconductor Memory. RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic. Memory Cell Operation.

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William Stallings Computer Organization and Architecture 7th Edition

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  1. William Stallings Computer Organization and Architecture7th Edition Chapter 5 Internal Memory

  2. Semiconductor Memory Types

  3. Semiconductor Memory • RAM • Misnamed as all semiconductor memory is random access • Read/Write • Volatile • Temporary storage • Static or dynamic

  4. Memory Cell Operation

  5. Dynamic RAM • Bits stored as charge in capacitors • Charges leak • Need refreshing even when powered • Simpler construction • Smaller per bit • Less expensive • Need refresh circuits • Slower • Main memory • Essentially analogue • Level of charge determines value

  6. Dynamic RAM Structure

  7. DRAM Operation • Address line active when bit read or written • Transistor switch closed (current flows) • Write • Voltage to bit line • High for 1 low for 0 • Then signal address line • Transfers charge to capacitor • Read • Address line selected • transistor turns on • Charge from capacitor fed via bit line to sense amplifier • Compares with reference value to determine 0 or 1 • Capacitor charge must be restored

  8. Static RAM • Bits stored as on/off switches • No charges to leak • No refreshing needed when powered • More complex construction • Larger per bit • More expensive • Does not need refresh circuits • Faster • Cache • Digital • Uses flip-flops

  9. SRAM v DRAM • Both volatile • Power needed to preserve data • Dynamic cell • Simpler to build, smaller • More dense • Less expensive • Needs refresh • Larger memory units • Static • Faster • Cache

  10. Read Only Memory (ROM) • Permanent storage • Nonvolatile • Microprogramming (see later) • Library subroutines • Systems programs (BIOS) • Function tables

  11. Types of ROM • Written during manufacture • Very expensive for small runs • Programmable (once) • PROM • Needs special equipment to program • Read “mostly” • Erasable Programmable (EPROM) • Erased by UV • Electrically Erasable (EEPROM) • Takes much longer to write than read • Flash memory • Erase whole memory electrically

  12. Organisation in detail • A 16Mbit chip can be organised as 1M of 16 bit words • A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on • A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array • Reduces number of address pins • Multiplex row address and column address • 11 pins to address (211=2048) • Adding one more pin doubles range of values so x4 capacity

  13. William Stallings Computer Organization and Architecture7th Edition Chapter 4 Cache Memory

  14. Location • CPU • Internal • External

  15. Locality of Reference • During the course of the execution of a program, memory references tend to cluster • e.g. loops

  16. Cache • Small amount of fast memory • Sits between normal main memory and CPU • May be located on CPU chip or module

  17. Cache/Main Memory Structure

  18. Cache operation – overview • CPU requests contents of memory location • Check cache for this data • If present, get from cache (fast) • If not present, read required block from main memory to cache • Then deliver from cache to CPU • Cache includes tags to identify which block of main memory is in each cache slot

  19. Cache Read Operation - Flowchart

  20. Typical Cache Organization

  21. Performace of Cache Systems • Let tc =cache access time h =hit ratio tm=memory access time Average access time ( AT ) = htc+(1-h)(tc +tm ) Ration of memory access time to cache access time (g )= tm / tc Efficiency = tc / AT Example Let tc =160 ns, tm=960ns, h=0.90 Calculate Effceincy, AT, and g AT=0.9*160 +(1-0.9)(960+160) 144+112=256 ns g = 960/160=6 Efficiency =160/256=0.625

  22. Direct Mapping • Each block of main memory maps to only one cache line • i.e. if a block is in cache, it must be in one specific place • Address is in two parts • Least Significant w bits identify unique word • Most Significant s bits specify one memory block • The MSBs are split into a cache line field r and a tag of s-r (most significant)

  23. Cache Memory Techniques • Fully Associative Mapping • Direct Mapping • Set Associative Mapping

  24. Fully Associative Mapping • In fully Associative Mapping, a main memory block i can be mapped to any cache block j.

  25. To determine which block of main memory is stored into cache, a tag is required for each cache block Tag(j)= address of memory block stored in cache block j ِAssume that M=2m then the tag should at least store the m bits When CPU generates an address, the main memory block is extracted and then associatively compared with the tags for a match. If a match occurs, the corresponding cache block number is retrieved and the cache is accessed for the required data

  26. Direct Mapping • To reduce the cost of the associated memory, direct mapping is used. The memory block i is always mapped into cache I mode N.

  27. Associative set • Instead of directly map the memory block into a certain block in the cache, the memory block can be mapped in a set of cache blocks. These blocks can be then associatively mapped.

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