Receivers Design: Cases Studies

1. Receivers Design: Cases Studies Edgar Sánchez-Sinencio TI J. Kilby Chair Professor Department of Electrical Engineering Analog and Mixed-Signal Center Texas A&M University http://amesp02.tamu.edu/~sanchez/

2. Outline • Brief Description of Receivers and Transceivers designed at the Analog and Mixed-Signal Center: 2000-2008 period • Bluetooth • System level design • Building blocks design detail • Dual standard Receiver: Chamaleon • Bluetoot and Wi-Fi ( 802.11b) • Systems and Building block considerations

3. Bluetooth Receiver Chameleon Receiver Radios Designed in AMSC 2000-2008 Ultra-Wideband Receiver ZigBee Transceiver Millimeter-wave Dual standard Receiver MICS Transceiver

4. What research has been done on wireless systems in AMSC ? • Bluetooth Receiver in 0.35um CMOS technology. (2001-2002) 6 Ph.D. students and one faculty were involved. • Chameleon: Bluetooth/Wi-Fi (802.11b) Receiver in 0.25um in SiGe IBM technology; (2002-2003) 7 Ph.D. students and one faculty were involved. • Ultra Wide Band Receiver in 0.25um SiGe IBM technology (2004-2005) with 4 Ph.D. students and two faculty members were involved. • Zigbee Transceiver in 0.18um TSMC (2004-2006) 1 MSc and 6 Ph D and one faculty are involved • MICS Transceiver in 0.13um UMC (2006-2008) 3 #Ph D students and two post-doctoral and one faculty are participating.

5. What is Bluetooth? • Bluetooth is a technology for small form factor, low-cost, short-range radio links between mobile PCs, mobile phones and other portable devices.

7. Overview of Bluetooth • 2.4GHz - 2.48 GHz ISM band. • GFSK modulation: index = 0.28 - 0.35. • 1 Mb/s data rate and 1 MHz channel spacing. • The market size for Bluetooth chip to be $4.3 billion by 2005 (Merrill Lynch) • The Bluetooth special interest group has signed up 2491 member companies

9. Bluetooth: System Level Design

10. Direct-Conversion Receiver DC offset and flicker noise problem: 99% of signal power is within DC to 430kHz. A fast settling AGC may be required for GFSK demodulation. Low-IF Receiver Greatly alleviated DC offset and Flicker noise problem. Relaxed image rejection requirement (~33 dB). Monolithic Receiver Architectures

11. Potential Receiver Architectures Low IF Receiver Architecture • High level integration and possible low power design. • Flicker noise less significant in signal band. • DC offset can be easily removed. • Image rejection. • Folded-back interference.

12. What other receiver structures alternatives can be considered and with what properties ? Can we make the IF very low, say to DC ? How and at what price ? Direct Conversion (IF=0)

13. Potential Receiver Architectures Direct Conversion Receiver • High level integration. • No image rejection required. • Less components, possible low power consumption • DC offset. • Flicker Noise.

14. Which architecture to choose? • Low IF is favored in specifications • Image interference exception alleviates the image rejection requirement • Flicker noise is hard to avoid in CMOS implementation • Alternative technology (e.g. SiGe) may perform better with direct conversion architecture • Low IF is the way to go for CMOS Bluetooth receiver!

15. Problems to Solve in Low IF Receiver • Choice of IF • Trade-off between having relatively high or low IF should be taken into consideration • Image rejection • +9dB image signal need to be suppressed • Folded-in interference rejection • It could be worse interferer than image signal

16. Problems to Solve in Low IF Receiver :Trade-off of IF • Lower IF • relaxed image rejection requirement • lower folded back interference level • lower Q requirement of the filter • lower power consumption of baseband blocks • Higher IF • improved FM demodulator performance • easily removed DC offset and less flicker noise • 2 MHz IF is chosen for a good compromise.

17. IRR > 60 dB Image Rejection :Active Complex Filter • Not like the traditional nonlinear lowpass to bandpass frequency transformation, linear frequency transformation, H(jw) ---> H(j(w-w0)obtain a complex bandpass filter. 5th Order Chebyshev Polypahse Filter

18. Folded-in Interference • Assuming IF is 2 MHz, a strong interference 5 MHz away from desired signal at RF is folded in to 1 MHz away at IF. The interference can be 40 dB higher than the signal. Channel select filter stopband attenuation requirement can be stringent.

19. Where is the Folded Interference ? • Assuming IF is 2 MHz, a strong interference 5 MHz away from desired signal at RF is folded in to 1 MHz away at IF. The interference can be 40 dB higher than the signal. Channel select filter stopband attenuation requirement can be stringent.

20. Receiver Noise Figure and IIP3 • Receiver sensitivity -85 dBm • Required SNR at baseband 15 dB • Noise Bandwidth 1.35 MHz • RF filter insertion loss 2.5 dB • Receiver Noise Figure 10.2 dB • Receiver IIP3 -14 dBm • Power Consumption <50 mA (3V supply)

21. Complete Receiver Diagram

22. Building Blocks DesignLNAMixerFrequency synthesizer & VCOActive complex filterLimiter & GFSK demodulatorDC offset tracking and canceling Low Noise Amplifier

23. LNA Design Target • Robust input matching • 50 Ohm input impedance to provide the termination for preceding external compents • High gain • Since LNA is the first block of the entire receiver, high gain of the LNA helps to reduce overall noise figure • Low noise • Noise figure of LNA sets lower bound of the system noise figure • Sufficient linearity, low power consumption

24. Inductive Source Degeneration Type LNA • Input impedance is proportional to Ls • Cascode (M1-M2) structure for high gain • M1, M2 must be optimized for lowest noise

25. On Chip Spiral Inductor • On chip spiral inductor is utilized for source degeneration (Ls) and inductive load (Ld) • Software ASITIC is used to characterize the on chip spiral inductor.

26. Simulation ResultsGain and Noise • Noise figure: 2.6 dB • Voltage gain: 18.2 dB

27. Building Blocks Design Mixer

28. Mixer Design Consideration • Different types of mixers are available • Passive mixer – lower power consumption • Active mixer – conversion gain reduces the requirement of LNA • Low noise design is still important since mixer is one of the front end block • Linearity requirement is higher than that of LNA

29. Schematic of the mixer • Double balanced Gilbert Cell mixer • Current injection to alleviate the trade off between the linearity and power supply voltage

30. Building Blocks Design Frequency Synthesizer

31. Frequency Synthesizer Design Target • Must be able to cover the entire band • Minimize power consumption • Make it as simple as possible – integer-N type • Settling time is relaxed in Bluetooth specification • No need for more complex fractional-N type PLL • The design of prescaler can be challenging since it has to work at carrier frequency

32. The Synthesizer Structure • An integer N architecture is preferred for the synthesizer to minimize power consumption • Current steering logic prescaler • Settling time 120ms • Phase noise 130dBc@3MHz

33. Prescaler Design • Current steering dividers are used in the prescaler to reduce power consumption

34. Synthesizer Simulations • Settling time: 120 s • Complete PLL transistor level simulation

35. Building Blocks Design Voltage Controlled Oscillator

36. VCO Design Target • Must be able to cover the entire band and some more to compensate process variation • Quadrature (I/Q) output is required for modulation • Tuning sensitivity must be high enough to cover the range but low enough to reduce noise due to control signal • Phase noise requirement came from third and higher interference specifications

37. VCO Schematics

38. Discrete Tunable Bank Varactor • The varactor has 2bit discrete tuning • They can provide 4 steps of coarse tuning range • Coarse tuning is mainly for compensating process variation

39. Building Blocks Design Complex Filter

40. How Does Complex Filter work? • Bandpass filter for signal side, attenuator for image side

41. How to implement complex filters? • Design a LPF prototype by frequency shifting the desired BPF response to DC • Frequency translation (ss-jwc), by replacing each integrator by its complex equivalent

42. How to implement complex filters? • For OTA-C filters, two cross coupled OTA’s are used • Butterworth approximation is preferred because: • good group delay response • all poles have the same magnitude • Equal C design • Equal cross coupled OTA’s • Good matching

43. Complex Filter Design Target • Image rejection depends on matching between I and Q branches (30dB image rejections requires 5% gain error and 3o phase error). • The LPF prototype is a 6th order Butterworth filter. The Corresponding BPF is 12th order. • Due to the tough noise requirements, a very simple OTA is used. • A simple input gain stage (15dB) is used to minimize the input referred noise • Large channel lengths (6mm) are used to minimize flicker noise, improve matching, improve linearity, and avoid using cascode transistors.

44. Complex Filter Overall Block Diagram • 6th order Butterworth approximation • Biquadratic OTA-C filter • Automatic frequency tuning by relaxation oscillator

45. Single BiQuad Stage • A Gm-C implementation. • Only the I side is illustrated, another part for the Q- part must be added.

46. OTA architecture • gm is controlled by the common mode voltage. • The CM voltage is stabilized using VCM • VCM is controlled by the common mode detector at the input (CMFF) or the output (CMFB) of the OTA.

47. Tuning Circuit • Only frequency tuning is required since the maximum Q in the filter is 2, which is low enough • The tuning circuit is run at 1MHz to minimize coupling to the complex filter

48. Complex Filter Measurement • Image Rejection Ratio 45dB • Signal side attenuation –27dBc, –58dBc • Image side attenuation-79dBc, -95dBc

49. Building Blocks Design GFSK Demodulator

50. Motivation to Build a Mixed-Mode Demodulator • AGC difficult to handle in frequency hopping system. • Short preample (4 symbols) requires extremely fast settling of AGC. • Constant envelope GFSK modulation allow use of simple limiting receivers and non-coherent detection. • By replacing AGC and ADC with a demodulator, power consumption can be lowered