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High Speed Signal/Data Transmission in BESIII Trigger and PANDA TDAQ Systems

I would like to thank Prof. Y. Sakai and Dr. Y. Iwasaki for their kind help in BESIII trigger design, and I am happy that we have this chance to share our experience of BESIII in KEKB Trigger and DAQ design. High Speed Signal/Data Transmission in BESIII Trigger and PANDA TDAQ Systems.

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High Speed Signal/Data Transmission in BESIII Trigger and PANDA TDAQ Systems

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  1. I would like to thank Prof. Y. Sakai and Dr. Y. Iwasaki for their kind help in BESIII trigger design, and I am happy that we have this chance to share our experience of BESIII in KEKB Trigger and DAQ design. LIU,Zhen'An, TriggerGroup,IHEP

  2. High Speed Signal/Data Transmissionin BESIII Trigger and PANDA TDAQ Systems Zhen’An LIU Trigger Group, IHEP Beijing 2nd Open meeting for the KEKB proto-collaboration July 3-4th 2008

  3. Outline • Background infor for BESIII trigger • Study of High speed signal transmission in BESIII trigger • BESIII trigger • PANDA TDAQ • Computer Node • Proof of Concept Application:HADES DAQ Upgrade • Comments and conclusion LIU,Zhen'An, TriggerGroup,IHEP

  4. Key points in BESIII trigger Design • Optical isolation with FEE, to prevent from ground loop current interference • Most latest FPGAs, Boards with simplicity, high reliability • FPGA online downloadable via VME • Generalized hardware, firmware for different function, for easy maintenance • Scheme optimization with simulation LIU,Zhen'An, TriggerGroup,IHEP

  5. Difficulties for MDC tracking Difficulties • Bad number of wires for both axial and stero layers (trigger point of view, Hard to define Sector/board border for signal input) • Hard to input signals via 9U front and rare pannels • Too many sharing signals for neighbor boards Solution: • RocketIO for input signals (32bits/ch, 8b/10b) • private VME J3 Backplane for sharing signals LIU,Zhen'An, TriggerGroup,IHEP

  6. Study of High speed signal transmission in BESIII trigger LIU,Zhen'An, TriggerGroup,IHEP

  7. MFT (MDC Fiber Transmitter) • 2796 hits signals from MDC QT boards are collected in MFT, 32 channels per MFT • Virtex-II Pro FPGA: XC2VP2 • Fuctions: • Stretching to 500ns • Synchronization + alignment signals(private Protocol) • Serialization(8b/10b) LIU,Zhen'An, TriggerGroup,IHEP

  8. TKF (TracK Finder) XC2VP40 : FF1152, 804 user IOs, 43,632 logic cells, 3,456Kbit BRAM, 12 RocketIOs, 2 PowerPCs, 192 multiplier blocks 10 layers 9UVME PCB • Functions: • Deserialization • Channel alignment • TSF • TF • Track information HFBR5921L XC2VP40 LIU,Zhen'An, TriggerGroup,IHEP

  9. Clock correction • K codes • COMMA • IDLE • RXRECCLK • RXUSRCLK LIU,Zhen'An, TriggerGroup,IHEP

  10. Data alignment • Continuous • Parallel bits transmitted in same clock => recovered also in same Clock • Special private protocol LIU,Zhen'An, TriggerGroup,IHEP

  11. Clocks • Crystal • Must follow the recommendation • Use built-in DCM • Clocks • REFCLK • USRCLK • USRCLK2 LIU,Zhen'An, TriggerGroup,IHEP

  12. Example of RocketIO Instantiation • RocketIO_1 : GT_CUSTOM • generic map( CRC_END_OF_PKT => "K29_7", • CRC_FORMAT => "USER_MODE", • CRC_START_OF_PKT => "K27_7", • TX_CRC_USE => TRUE, • TX_DATA_WIDTH => 4, • … ); • port map ( REFCLK=>REFCLK_IN, • TXUSRCLK=>TXUSRCLK_IN, • TXUSRCLK2=>TXUSRCLK2_IN, • TXCHARISK(3 downto 0)=>TXCHARISK_IN(3 downto 0), • TXDATA(31 downto 0)=>TXDATA_IN(31 downto 0), • TXFORCECRCERR=>TXFORCECRC_IN, • TXN=>TXN_OUT, • TXP=>TXP_OUT, • … ); LIU,Zhen'An, TriggerGroup,IHEP

  13. Transmission protocol • Transmitter side • Receiver side LIU,Zhen'An, TriggerGroup,IHEP

  14. Good reliability with RocketIO MGT MGT HFBR5921L HFBR5921L TD+ TXP TXP TD+ TD- PRBS Data Generate TXN TXN Data Aligned & Checker TD- RD TD TD RD TXDATA (31:0) RXDATA (31:0) RD+ RXP RXP RD+ RD- RXN RXN RD- FPGA FPGA MFT TKF Tx Data Total periods # of errors Rx random data Rx data errors 1 BER ＝ < ≈ 8.3×10-16 periods × 40 3.0×10e13 × 40 LIU,Zhen'An, TriggerGroup,IHEP

  15. 128 Long Track Counter 3 MDC Trigger Conditions 80 ch Track Finder ×1 LTKC 9 MDC Fiber Transmitter 128 MDC Q&T Short Track Counter 4 1.75Gb/s ×8 TKF TO GTL ×96 Optical Channels Inner- layer Track Finder 16 ch ×1 STKC ×96 MFT 2 MDC Electronic Crates ×1 ITKF MDC Trigger Crate Type of PCB Board name # of boards FPGA firmware MTB MDC Fiber Transmitter 1 MFT 96 1 TracKFinder 1 ITKF 1 1 TKF 8 8 TracKCounter 1 LTKC 1 1 STKC 1 1 MDC Trigger Backplane 1 MTB 1 ITKF TKF Total 4 6 108 12 MDC Sub-Trigger LIU,Zhen'An, TriggerGroup,IHEP

  16. BESIII trigger Block diagram Near Detectors Counting Room Fast Control FC Daughters High Lights: Optical Isolation-no ground loop current Global Trigger Logic TOF FEE TOFPR Hit/Seg Count Track Match MDC FEE MFT TSF + TF Track Counter TKF Energy Balance EMC FEE TCBA TC Sum Etotal Energy L1P Cluster Counting TKF MU FEE FastOR Mu track TKF BEPCII RF TTC 499.8 MHz 41.65 MHz 6.4 s LIU,Zhen'An, TriggerGroup,IHEP

  17. Installation MFTs in FEE crate Jumper Box LIU,Zhen'An, TriggerGroup,IHEP

  18. TOFPR LIU,Zhen'An, TriggerGroup,IHEP

  19. Installation TCBA: EMC preprocessor and transmitter LIU,Zhen'An, TriggerGroup,IHEP

  20. CLK + FC Installation cont’d TDC MDC Trigger EMC/TOF/GTL Trigger Optical Fibers Optical Cables Opt-Cable under LIU,Zhen'An, TriggerGroup,IHEP

  21. Status of BESIII trigger • Successful in Cosmic-ray test • Commissioning with BEPCII LIU,Zhen'An, TriggerGroup,IHEP

  22. PANDA: DAQ Requirements Interactions: 10**7 Hz Data: 200GB/s Continuously Sampling ADC No hardware trigger Hi Speed Devices Large Buffers Large Bandwidth LIU,Zhen'An, TriggerGroup,IHEP

  23. PANDA DAQ & Trigger • 2 Alternative DAQ Concepts Still Under Discussion Detector’s Front-end Concentrator Board L1out L2out L3out Switch Switch Switch L1 farm L2 farm L3 farm LIU,Zhen'An, TriggerGroup,IHEP

  24. The Compute Node(CN) • 5 Virtex4 FX60 FPGA • Large Computer Power • 10 GB DDR2 RAM (2GB per FPGA) • Buffering capabilities • 2 Embedded PowerPC in each FPGA • Slow control • 32Gbit/s Bandwidth • 13x RocketIO to backplane • 5x Gbit Ethernet Front Pannel • 1x Gbit Ethernet Backplane • 8x Optical Links • ATCA Compliant • Manageability LIU,Zhen'An, TriggerGroup,IHEP

  25. The Compute Node LIU,Zhen'An, TriggerGroup,IHEP

  26. Prototype of the CN by IHEP Beijing • Backplane • FPGA #O • FPGA #1-4 • Front Panel • Optical Links • Ethernet Plugs LIU,Zhen'An, TriggerGroup,IHEP

  27. Proof of Concept Application:HADES DAQ Upgrade • Est.: 2009 • Read Out – Trigger • TRB • Faster Readout • Trigger and Data • Optical Links • Include Tracking in Trigger • 12 Compute Node • 1 Full ATCA shelf COMPUTE NODE • Online Tracking • RICH & TOF • Matching with Tracking • Event Building on FPGA • Others • Remote Upgrade • IPMI LIU,Zhen'An, TriggerGroup,IHEP

  28. Motivation/Aim Produce a Configurable and Scalable Hardware Platform for Multiple Applications & Experiments • Capable of High Performance Computing • Large Bandwidth • Real Time processing • Trigger • Flexibility: Reusable • HADES - BESIII - PANDA • Scalability • Flexible network topology LIU,Zhen'An, TriggerGroup,IHEP

  29. Comments and Conclusion • RocketIO can be used for HS transmission at KEKB • Awareness to KEKB TDAQ design: • System clock • Larger trigger latency • Latency by RocketIO (SEDES takes time ) • Needs larger pipeline buffer in FEE • Synch. + alignment • Uncertainty in recovered clock • Opt-cable length difference • Opt-transceiver difference LIU,Zhen'An, TriggerGroup,IHEP

  30. Thanks! LIU,Zhen'An, TriggerGroup,IHEP

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