Design & Co-design of Embedded Systems

1. Design & Co-design of Embedded Systems Introduction to Co-synthesis Algorithms + HW/SW Partitioning Algorithms Maziar Goudarzi

2. Today Program • Introduction • Preliminaries • Hardware/Software Partitioning • Distributed System Co-Synthesis (Next session) Reference: Wayne Wolf, “Hardware/Software Co-Synthesis Algorithms,” Chapter 2, Hardware/Software Co-Design: Principles and Practice, Eds: J. Staunstrup, W. Wolf, Kluwer Academic Publishers, 1997. Design & Co-design of Embedded Systems

3. Introduction to HW/SW Co-Synthesis Algorithms Introduction

4. Introduction • Implementing a system? Why use CPU? • Easier implementation • Easier (and cheaper) to change and debug • Why use hardware modules? • Meeting other constraints • performance, power consumption, etc • Found a CPU meeting all non-functional constraints? • Yes! What could be better? Use the CPU. • No! Design custom logic, or a combination of both Design & Co-design of Embedded Systems

5. Introduction (cont’d) • Why more than one CPU or custom logic? • Why not use the fastest available CPU? Design & Co-design of Embedded Systems

6. Introduction (cont’d) • Reason 1: • Exponential cost per CPU performance • Figure: • late-1996 retail prices of Pentium Processor Clock speed(MHz) Pentium processor prices Design & Co-design of Embedded Systems

7. Introduction (cont’d) • Exponential price/performance implies • Paying for performance in a uni-processor is very expensive • Using multiple small CPUs is cheaper • Communication overhead is added, but still an economic choice • Processors need not be CPUs. But special-function units. • Special-purpose PEs can be even cheaper than dedicated CPU! • Measured in system manufacturing cost, not necessarily in design cost Design & Co-design of Embedded Systems

8. Introduction (cont’d) • Reason 2: • Scheduling overhead • More than 31% overhead, under reasonable assumptions, when executing multiple processes • Reason: uncertainty in the times at which the processes will need to execute • Result: we have to reserve extra CPU horsepower, which comes at exponential cost Design & Co-design of Embedded Systems

9. Introduction (cont’d) • Definition • HW/SW co-synthesis: process of simultaneously design the SW architecture of an application and the HW architecture on which that SW is executed. Design & Co-design of Embedded Systems

10. SW(app.)Arch. CoSynthesis Communication Channels HW Engine PE PE PE Mem Introduction (cont’d) ProblemSpecification Design & Co-design of Embedded Systems

11. Introduction (cont’d) • Problem specification includes • Functionality • Non-functional requirements • Performance goals, physical constraints, etc Design & Co-design of Embedded Systems

12. Introduction (cont’d) • Hardware Architecture • One or more Processing-Elements (PEs) • Software (Application) Architecture includes • Process structure • Each process executes sequentially • Determines • The amount of parallelism • The amount of communication • Proper process structure is crucial for cost-effective implementation • Allocation of the processes onto PEs in the HW engine • Communication channels • Hardware elements • Software primitives Design & Co-design of Embedded Systems

13. Introduction (cont’d) • HW/SW Co-synthesis • Allows trade-offs between SW architecture and HW on which it executes • Where is such trade-off important? • Everyday processing applications vs. Embedded applications • Embedded computing: Computing with limited resources • Different co-synthesis styles depending on • The Specification • The System Components • System Elements to synthesize Design & Co-design of Embedded Systems

14. Introduction (cont’d) • Two broad implementation styles • HW/SW partitioning • Target HW architecture: a CPU and multiple ASICs • Distributed System Co-synthesis • Target HW architecture: arbitrary hardware topologies Design & Co-design of Embedded Systems

15. Introduction to HW/SW Co-Synthesis Algorithms Preliminaries

16. Preliminaries • Rate (execution rate) • Maximum frequency at which a processing must be done • Single-rate vs. Multi-rate • Example of multi-rate system • audio/video decoder Design & Co-design of Embedded Systems

17. Preliminaries (cont’d) • Latency • Required maximum time between starting and finishing a processing task Design & Co-design of Embedded Systems

18. Behavior Models • DFG: Data Flow Graph • Suitable for data-processing algorithms • CFG: Control Flow Graph • Suitable for process control algorithms • CDFG: Control Data Flow Graph • Combination of the two above Design & Co-design of Embedded Systems

19. Behavior Models (cont’d) • Single-rate systems • Standard model: Control-Data Flow Graph (CDFG) • Implies a program-counter or system-state • Not suitable to model multi-rate tasks • Due to unified system state Design & Co-design of Embedded Systems

20. P4 P5 P6 Behavior Models (cont’d) • Multi-rate systems • Common model: Task Graph • Task Graph • Each Node: Process • Each Edge: Communication • Each Set of connected nodes: sub-task P1 P2 P3 Design & Co-design of Embedded Systems

21. Behavior Models (cont’d) • SDFG: Synchronous Data Flow Graph • Suitable for signal processing applications • = DFG + may be cyclic • Lee and Messerschmitt: • Algorithm to check feasibilityof an SDFG + schedule it ona uni-processor or multiprocessor 1 2 a b 1 1 2 c 1 Design & Co-design of Embedded Systems

22. Behavior Models (cont’d) • Co-design Finite-State Machine (CFSM) • POLIS project at UC-Berkeley • Used for control-dominated systems • e.g., ECU (Engine Control Unit) • Event-driven FSM • Transitions occur by events (instead of periodic clock signal) Done/stop_time idle test Go /start_timer Reset/ alarm=OFF Timeout/alarm=ON error Design & Co-design of Embedded Systems

23. Architectural Models • The hardware engine also needs a description • Here, only basic models for cost estimation Design & Co-design of Embedded Systems

24. Architectural Models (cont’d) • HW-engine is another graph • Generally: • Processing Elements (PE) as nodes + communication channels as edges • Problem: How to model busses? • Solution: • Nodes also used for channels • Edges represents nets connecting PEs and channels • Nodes are labeled with their type Design & Co-design of Embedded Systems

25. Architectural Models (cont’d) • Component Technology Library • Used when pre-designed components constitute the HW engine • Includes • General parameters • e.g., manufacturing cost, average power consumption, clock rate • Information regarding functional elements (behaviors) • A table giving execution time of each behavior on that PE Design & Co-design of Embedded Systems

26. Architectural Models (cont’d) • CPU scheduling • Process vs. thread (light-weight process) • We use these terms interchangeably • Scheduling policies to run multiple processes on a single CPU • Non-preemptive vs. preemptive (prioritized) • Time-slicing not normally used in embedded systems Design & Co-design of Embedded Systems

27. Architectural Models (cont’d) • Scheduling policies (cont’d) • Priority can be static or dynamic • A well-known static priority scheme: • RMS (Rate monotonic Scheduling) • Best static schedule • Guarantees all deadlines • Needs 31% extra CPU horsepower • A well-known dynamic priority scheme: • EDF (Earliest Deadline First) • 100% CPU utilization • May miss deadlines • More on this later Design & Co-design of Embedded Systems

28. Topics • Introduction • Preliminaries • Hardware/Software Partitioning • Distributed System Co-Synthesis Design & Co-design of Embedded Systems

29. Topics • Introduction • A Classification • Examples • Vulcan • Cosyma Design & Co-design of Embedded Systems

30. Introduction to HW/SW Partitioning • The first variety of co-synthesis applications • Definition • A HW/SW partitioning algorithm implements a specification on some sort of multiprocessor architecture • Usually • Multiprocessor architecture = one CPU + some ASICs on CPU bus Design & Co-design of Embedded Systems

31. Introduction to HW/SW Partitioning (cont’d) • A Terminology • Allocation • Synthesis methods which design the multiprocessor topology along with the PEs and SW architecture • Scheduling • The process of assigning PE (CPU and/or ASICs) time to processes to get executed Design & Co-design of Embedded Systems

32. Introduction to HW/SW Partitioning (cont’d) • In most partitioning algorithms • Type of CPU is fixed and given • ASICs must be synthesized • What function to implement on each ASIC? • What characteristics should the implementation have? • Are single-rate synthesis problems • CDFG is the starting model Design & Co-design of Embedded Systems

33. HW/SW Partitioning (cont’d) • Normal use of architectural components • CPU performs less computationally-intensive functions • ASICs used to accelerate core functions • Where to use? • High-performance applications • No CPU is fast enough for the operations • Low-cost application • ASIC accelerators allow use of much smaller, cheaper CPU Design & Co-design of Embedded Systems

34. A Classification • Criterion: Optimization Strategy • Trade-off between Performance and Cost • Primal Approach • Performance is the primary goal • First, all functionality in ASICs. Progressively move more to CPU to reduce cost. • Dual Approach • Cost is the primary goal • First, all functions in the CPU. Move operations to the ASIC to meet the performance goal. Design & Co-design of Embedded Systems

35. A Classification (cont’d) • Classification due to optimization strategy (cont’d) • Example co-synthesis systems • Vulcan (Stanford): Primal strategy • Cosyma (Braunschweig, Germany): Dual strategy Design & Co-design of Embedded Systems

36. Co-Synthesis Algorithms:HW/SW Partitioning HW/SW Partitioning Examples: Vulcan

37. Partitioning Examples:Vulcan • Gupta, De Micheli, Stanford University • Primal approach 1. All-HW initial implementation. 2. Iteratively move functionality to CPU to reduce cost. • System specification language • HardwareC • Is compiled into a flow graph Design & Co-design of Embedded Systems

38. x=a; y=b; HardwareC nop 1 1 x=a y=b cond c>d c<=d if (c>d)x=e;else y=f; HardwareC x=e y=f Partitioning Examples:Vulcan (cont’d) Design & Co-design of Embedded Systems

39. Partitioning Examples:Vulcan (cont’d) • Flow Graph Definition • A variation of a (single-rate) task graph • Nodes • Represent operations • Typically low-level operations: mult, add • Edges • Represent data dependencies • Each contains a Boolean condition under which the edge is traversed Design & Co-design of Embedded Systems

40. Partitioning Examples:Vulcan (cont’d) • Flow Graph • is executed repeatedly at some rate • can have initiation-time constraints for each node t(vi)+lij t(vj)  t(vi)+uij • can have rate constraints on each node mi  Ri  Mi Design & Co-design of Embedded Systems