EDP - 2001 CONFERENCE Session 7: Analog and Analog-mixed-signal (A/AMS) Design Flows Current Analog Design Methodologies

1. EDP - 2001 CONFERENCESession 7: Analog and Analog-mixed-signal (A/AMS) Design FlowsCurrent Analog Design Methodologies and Practices Bill Guthrie Numetrics Management Systems, Inc. April 10, 2001

2. Investigating Analog & Mixed-Signal Design Practices • What is the definition of an analog or mixed-signal chip? • How do AMS chip design projects compare to SoC design projects? • What is the AMS content of an SoC design? • Are AMS blocks increasing in size? • Is AMS design productivity increasing? Data from Numetrics’ Design Productivity Management System database is used to investigate these issues.

3. DPMS Database Used in This Investigation Design Projects Accumulated in the DPMS Database 400 368 Projects As of 27-Mar-01 350 300 250 ASIC Projects No. of Designs 200 150 100 ASSP Projects 50 0 1998 1999 2000 Data Capture Date

4. Companies Represented in the DPMS Database

5. Characteristics Used to Define & Select AMS Projects in the DPMS Database • Projects are included if one of the following criteria is met • Analog circuitry contains ≥ 1,000 transistors • RF circuitry is used • Analog or Mixed-Signal circuitry comprises more than 10% of all transistors • BiCMOS or Bipolar process is used • Large geometry process is used (≥ 0.6 micron) • Only 1 metal layer is used • Projects are excluded if one of the following criteria is met • Design style is “Gate Array” or “Embedded Array” • No Analog, Mixed-Signal, or RF circuitry is used • Small geometry process is used (≤ 0.25 micron) • High layer count metal system is used (≥ 5 layers)

6. Physical New Reuse Circuitry New 35% Circuitry 41% Physical 33% Reuse 45% Logical Logical Reuse Reuse 22% 24% Comparison of AMS and SoC Projects CYCLE TIME TEAM SIZE 12.7 73 Weeks 49% SoC 51% PEAK FTE 1st Tape-out 4.5 54 Weeks AMS 39% 61% SoC AMS SIZE, REUSE & COST SoC: 4.9M Transistors $2.5M Development Cost AMS: 330K Transistors $780K Development Cost Projects were started in 1998 or later. Sample size is 112 projects.

7. AMS Content in SOC Designs SoC BREAKDOWN BY CIRCUIT TYPE AVERAGE SoC BLOCK COUNT Analog & Mixed-Signal 0.5% Average Number of Blocks: 12.50 Analog 0.86 DSP & Comm Logic & Datapath 21.7% 1.49 Memory 2.10 Mixed Signal 2.60 Interface 2.65 Memory 77.8% CPU & Control 2.81 0.00 0.50 1.00 1.50 2.00 2.50 3.00 Number of Functional Blocks Average Size = 4,900,000 Transistors AMS Content = 24,000 Transistors Based on 72 designs started in 1998 or later

8. 1- 21- 41- 61- 81- 20% 40% 60% 80% 99% New Circuitry Logical Reuse Physical Reuse AMS Block Size Growth is Due to Reuse AMS Block Size & Effort Total Reuse per AMS Block 4,210 4,200 CAGR = 33% 1,172 48% 50% 40% 708 2,396 2,400 Transistor Count Frequency 30% 1,178 19% 20% 2,330 13% 11% 538 10% 6% 680 2% 1% 0% 0% 1997-1998 0% 100% 1999-2000 Effort = 16.3 Effort = 13.6 Percentage of Circuitry Reused (Projects started 1999-2000) (Person-weeks) (Person-weeks) Based on sample of 400 AMS blocks

9. AMS Block Design Productivity Trend 100% Reused AMS Blocks 3,000 2,630 2,500 CAGR = 97% 2,000 Transistors per Person-week 1,500 All New AMS Blocks 1,000 677 CAGR = 33% 500 165 80 0 1997- 1998 1999- 2000 1997- 1998 1999- 2000 Productivity does not include adjustments for circuit complexity or effortfor chip-level or project-level development tasks.

10. Conclusions • AMS Projects are substantially smaller in scope than SoC projects • 25% shorter cycle times • 65% smaller teams • 69% lower development cost • SoC designs contain miniscule amounts of AMS circuitry on a percentage transistor basis, but on a block-count basis AMS represents over one-fourth of the design. • AMS blocks have grown in size by 33% per year, but all the growth is due to reused circuitry. • The productivity of raw AMS transistor design has increased • 33% per year for NEW AMS circuitry • 97% per year for REUSED AMS circuitry • REUSED AMS circuits require only 6% of NEW AMS circuit design effort