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Update on WP6: Interconnect work

Update on WP6: Interconnect work. S . Vähänen & M. Campbell 12 th March 2010. Interconnect. Personnel: 20% engineer (M. Campbell) CERN Fellow (Sami Vähänen) Marie Curie Early Stage Researcher (Timo Tick) Focus: Low-cost bump bonding

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Update on WP6: Interconnect work

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  1. Update on WP6: Interconnect work S. Vähänen & M. Campbell 12th March 2010

  2. Interconnect Personnel: • 20% engineer (M. Campbell) • CERN Fellow (Sami Vähänen) • Marie Curie Early Stage Researcher (Timo Tick) Focus: • Low-cost bump bonding • Integration of through silicon vias (TSV’s) on CERN chips + complementary process steps • Chips with TSVs need to be joined to carrier boards in reliable way (BGA joint study)

  3. Outline • Low cost bump bonding activity • CERN test vehicle wafers • Maskless under bump metallization (UBM) deposition • Novel solder ball placement methods • Anisotropic conductive adhesive (ACF) as a replacement for solder • Flip chip assembly and electrical testing of devices • Carbon nanofibres – ultra low mass bumps • Through Silicon Via development • Progress at VTT • BGA processing ROC ROC ROC ROC ROC

  4. Low-cost bump bonding - introduction • Bump bonding (BB) costs for a single detector unit have been over € 200 - 300 • Readout chip (ROC) : sensor chip (SC) : bump bonding (cost ratio) = 1:2:7! • More pixel detectors are desired to be used in SLHC and the total area will cover tens of square meters- the cost issues is evident. • BB technology used in CERN pixel detectors is not commonly available in small volumes and it has lead to overpricing. Flip chip assembly part has caused the rise in total costs during last two years (pie diagrams). • Electroless under bump metallization (UBM), solder ball placement solutions, anisotropically conductive adhesives and carbon nanofibers are studied to substitute traditional bumping process.

  5. CERN Test Vehicle wafers • Test vehicle was designed to serve the low-cost flip chip, TSV and large area tiling development work. • Test vehicle has daisy chain and Kelvin test structures to characterize the interconnection yields and resistances at three interfaces: • Flip chip bumps (≈ 21 k/chip) • TSV’s (196/chip) • BGA joints (100/chip) • Test chips can be used for gathering reliability data during accelerated thermal stress testing. • 24 silicon wafers were processed at VTT (by Sami and Timo) to evaluate electroless UBM deposition, low-cost flip chip techniques and BGA connections. • Probe card for test vehicle has been produced and probing setup for assembled devices is being finalized.

  6. Under Bump Metallization (UBM) • Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) was processed on CERN test vehicle wafers by PacTech (DE) . This is a low cost and high volume capable process (mask free). • ENEPIG UBM is a good platform for various flip chip tests. • UBM will be characterized on test vehicle wafers and real CMOS wafers. • Some individual Medipix2 chips were also processed • There might be interests for single chip prototyping? ENEPIG UBM on Medipix2 chip ENEPIG UBM on CERN test vehicle chips

  7. Al wire bonding tests on ENEPIG pads • Electroless UBM can be grown on all the exposed Al on the wafers. • Masking may be necessary (dicing lanes and probing pads) • Al wire bonding experiments were carried out on 6 samples with ENEPIG metals with two separate parameter sets (tables below). • Chips with different plating quality were selected for the tests • Bright = smooth metal layer topography • Dark = rougher metal layer topography Thanks to Ian McGill Equal pull forces to Al-Al bonding Pulls strengths with less deformed Al wire Pull strengths with more deformed Al wire

  8. Solder ball placement methods – solder “spitting” process • Solder ball transfer methods in combination with ENEPIG will be tested because of their potential for • Low-cost solder bumping • High throughput • High yields – defected balls/shorts can be replaced • The solder ‘spitting’ process uses a nozzle combined with a high-powered laser to instantly heat and to drop the molten solder balls in place one by one in sequence. • Slow process (≈ 10 balls/s), but it may be appropriate for single chip (no complete wafers) prototyping in combination with ENEPIG UBM. • Process used in industry for placing BGA-like bumps on wafers for moderate volume production. Technique has relatively low NRE costs. • Prefabricated solder balls are directly dropped on the UBM – no mechanical contact to wafer.

  9. Solder ball transfer methods - “Gang ball’ placement • Gang ball placement technique uses a full sized wafer mask with predefined holes to transfer all balls of one wafer at the same time. • Potential to be very low cost per wafer • Process used in industry for bumping wafers for high volume production. • Limited by ball size • minimum 60 mm at present therefore suitable for 100 mm pitch • PacTech foresees 50 mm bumps in coming years • Tests foreseen at 110 mm pitch with CERN test vehicle wafers. • Status – an offer has been requested.

  10. Flip chip tests • Preliminary test program as follows: • Electroplated solder-to-solder flip chip (good reference, close to 100% yields) • Solder bumps bonded on ENEPIG UBM pads (in air ambient) • Solder bumps bonded on ENEPIG UBM pads (in reducing gas) • ACF film bonded in between chips with ENEPIG pads • 44 assemblies have been built so far (by Sami and Timo at VTT and SET, St. Jeoire) electrical tests and destructive tests pending • Future actions: • Solder bumps bonded on real CMOS chips with ENEPIG pads Electroless ENEPIG pad Picture: Detached ENEPIG pad after separation of assembled chips (in formic acid ambient). FC bonded solder bump Electroplated Ni UBM + solder

  11. Summary – Low-cost bump bonding • ENEPIG maskless process seems to work well on test wafers and on real chips. Results being confirmed now with ENEPIG deposition on full real CMOS wafers. • ENEPIG deposition is compatible with wire bonding. • Flip chip assembly between dummy ENEPIG readouts and conventional solder bumps on test sensor successful. • Only the sensor wafer would require expensive electroplating • Flip chip assembly of ENEPIG-ENEPIG devices using ACF being tested.

  12. Carbon nano-fiber (CNF) • Smoltek has delivered the first CERN test vehicle chips with CNF’s • We are looking into a common project for developing ultra-high-density (ultra-low mass) flip chip process with CNF’s. • CNF’s were deposited at 400 ˚C (relatively low-temperature process) • Test samples were analyzed and process issues were identified • New process tests with improved cycle coming in early summer • Smoltek will make offer for work on test vehicle and real devices. CNF forests on CERN test vehicle chips

  13. TSV development with VTT • This project is not included in the work package, but the subject is relevant. • Joint development project started in July 2009 (funding 50% Medipix Collaboration 50% VTT internal). Goal via-last process for Medipix wafers. • Detailed process description was agreed with VTT and CERN. • Development of process is started with 6” dummy wafers although CERN wafers are 8” • Test vehicle layout is used to process test chips for yield and quality evaluation • New 8” compatible process is under development. Planned timetable for the TSV project (deliverables with red font accomplished) Tapered TSV’s with top diameter of 66µm, depth 118 µm & 75 µm pitch.

  14. Summary - TSV project with VTT • VTT has received parylene tool which can be used for redistribution layer. • Wafer etching processes have been successfully transferred from 6” to 8” wafers. • VTT is able to seed and electroplate on tapered vias. • The goal is to use a 5 µm thick Cu liner on via sidewalls instead of completely filled TVS’s. • Easier process, less thermal stresses and good for demonstrating TSV’s • A new person has joined VTT’s TSV development team.

  15. Tests with BGA chips – update (1/2) • Basic BGA study is done in parallel with TSV study. • Timo manufactured a batch of LTCC boards at University of Oulu, Finland. • Silicon chips with ENEPIG UBM to be soldered on LTCC boards. • Yield measurements and reliability tests in accelerated environmental conditions • CERN test vehicle BGA interface to be tested with different carrier boards. • 3 different BGA bump types were chosen for evaluation: • Collapsible BGA - standard technique, reference • Land Grid Array (LGA) - simplest and cheapest solution, reliability needs to be proved • Non collapsible plastic core BGA (PCBGA) – a light-weight solution, radiation hardness to be proved PCBGA BGA LGA Sketches of different BGA joint scenarios

  16. Tests with BGA chips (2/2) • Measurement setup under construction. • 3 x 3 array of Si chips assembled on carrier board • 100 joints on each chip • 2 daisy chain structures on chips (outer/inner loop) • Two boards ready (BGA and LGA bumps – picture below) • Lifetime measurements (No. of cycles) in environmental chamber • Tests according to JEDEC and IPC standards • BGA bumping and device assembly done at CERN SMD laboratory. BGA LGA Assemble chips on LTCC boards in real life

  17. Outlook for interconnect work – Short term • Further studies of ENEPIG - ENEPIG flip chip process using ACF. • Start measuring electrical yields on daisy chains of CERN test vehicle assemblies. • ENEPIG deposition and solder ball placement serviced ordered on real Timepix wafers. Solder ball “spitting” (SB2) will be used for 55 mm and 110 mm pitches. • Try gang ball placement on CERN Test Vehicle at 110 mm pitch. • Optimize CNF growth process. • Build measurement setup for BGA assemblies and evaluate BGA reliability at Si-ceramic interface. • Continue studying different flip chip methods and equipment to lower the assembly costs. • Follow TSV development at VTT. Evaluate quality.

  18. Outlook for interconnect work – Medium term • Need for input from LHC experiments on future plans/needs • Low cost bump bonding (expected quantities, pitches etc) • TSV • Strategy group needed? • Depending on the outcome of the ENEPIG low cost bumping tests, there may be an interest in developing a facility for flip chip assembly of pixel detector prototypes at CERN • Follow developments in the microelectronics industry and, if needed, find a common access point for HEP community to TSV wafer post processing • Last point may be linked to AIDA effort on accessing a common TSV supplier

  19. THE END Thank you for your attention!

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