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Progress Update

Explore the advancements in Spin-Transfer Torque Random Access Memory (STT-RAM) with magnetic tunnel junctions (MTJ) and CMOS circuit design. Learn how STT-RAM overcomes limitations of existing memory technologies beyond 45nm, offering a blend of benefits from DRAM, SRAM, and Flash. Discover the challenges, solutions, and performance enhancements in STT-RAM cell structures and memory arrays.

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Progress Update

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  1. Progress Update STT-RAM Design Fengbo RenAdvisor: Prof. Dejan Marković Dec. 3rd, 2010

  2. Background • STT-RAM: Spin Transfer Torque Random Access Memory • Key memory device: magnetic tunnel junctions (MTJ) • R/W circuit: CMOS • Most existing memory technology is greatly challenged beyond 45 nm • SRAM: high power consumption, leakage increasing 10X with each technology node • DRAM: refresh current increasing, capacitor element hardly can maintain the necessary charge. • Flash: limited endurance, high write power, very slow write speed. • Need for universal memory Anti-parallel Parallel RP RAP

  3. Memory Technology Comparison • STT-RAM combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance.

  4. Cell Size • Cell structure • 2T-1MTJ • 1T-1MTJ • 1T-N MTJ??

  5. MTJ Sharing • Problem • Unexpected DC current paths through every MTJ. • Accidental switching in R/W • Parasitic resistance in parallel with the accessed MTJ • Reading error • Conclusion • Not going to work if M>2, M is # of MTJs shared by transistor • M = 2, N>8, significant TMR degradation • When RP = 500Ω, TMR = 120%, M = 2, N = 4 • TMR’ = 45%, might be able to read. • MTJ with higher RP and TMR, error correction coding will help • 1T-1MTJ & MTJ-sharing (M=2, N=64) memory arrays are implemented.

  6. 1T-1MTJ Memory Cell 65-nm 45-nm • Layout view • Min cell size (constrained by design rule) • F is min. space between x1 metal wire 65-nm 45-nm 0.55 um 0.405 um 0.5 um 0.38 um M4 C1 C1

  7. Write • P->AP • Vgs_P= VWL - Vdrop ≈ VDDW • Vds_P = VDDW – Vdrop – Vmtj_P • AP->P • Vgs_AP = VWL – Vdrop – Vmtj_AP • Vds_AP= VDDW - Vdrop – Vmtj_AP • Boosting VWL • Limited by Vgs_P (0.1 V margin) • Boosting VDDW • Limited by Vds_AP (0.5-0.6 V margin) • Have to use thicker oxide devices in the write driver circuit (in red)

  8. Write Current Comparison • Compare 3 cases of boosting voltage • Constraints • VDDW < VDDmax • Vgs, Vds < VDDmax • For all devices

  9. Write Current Comparison Result • Boost up VDDW to 1.1V, VWL to max - 21-22% gain • Boost up VDDW to 1.5V, VWL to max - 30-33% gain • Medium oxide device used, 2.2x bigger write driver • Boost up VDDW to 1.9V, VWL to max - 35-37% gain • Thick oxide device used, 7.6x bigger write driver

  10. Boost up VDDW • If thin oxide devices are used in write driver • Can not meet Vds constraint! • Medium oxide devices have to be used in write driver and mux. • So case 2 is the best, case 3 has too much area overhead

  11. Boost up VWL, dualVWL (VWL_P , VWL_AP) • On the addressed WL, cells on un-addressed column can not meet Vgs constraint • BL and SL of un-read/write column have to be kept on a positive voltage level of Vidle.

  12. Result after boosting VDDW & VWL • Medium oxide 1.5V high-speed IO device used in write driver, VDDW = 1.65V • Vidle = Vprecharge = 0.55V • Support VWL boosting up to 1.65V

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