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Data types Timing in VHDL

ECE 545 Lecture 13. Data types Timing in VHDL. Sources & Required Reading. Peter Ashenden, The Designer’s Guide to VHDL , Chapter 2 Scalar Data Types and Operations Chapter 4 Composite Data Types and Operations. VHDL as a Strongly Typed Language. Notion of type.

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Data types Timing in VHDL

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  1. ECE 545 Lecture 13 Data types Timing in VHDL ECE 545 – Introduction to VHDL

  2. Sources & Required Reading • Peter Ashenden, The Designer’s Guide to VHDL, • Chapter 2 • Scalar Data Types and OperationsChapter 4 • Composite Data Types and Operations ECE 545 – Introduction to VHDL

  3. VHDL as a Strongly Typed Language ECE 545 – Introduction to VHDL

  4. Notion of type • Type defines a set of values and a set of applicable operations • Declaration of a type determines which values can be stored in an object (signal, variable, constant) of a given type • Every object can only assume values of its nominated type • Each operation (e.g., and, +, *) includes the types of values to which the operation may be applied, and the type of the result • The goal of strong typing is a detection of errors at an early stage of the design process ECE 545 – Introduction to VHDL

  5. Example of strong typing architecture incorrect of example1 is type apples is range 0 to 100; type oranges is range 0 to 100; signal apple1: apples; signal orange1: oranges; begin apple1 <= orange1; end incorrect; ECE 545 – Introduction to VHDL

  6. Type Classification ECE 545 – Introduction to VHDL

  7. Classification of data types ECE 545 – Introduction to VHDL

  8. Integer Types ECE 545 – Introduction to VHDL

  9. Integer type Name:integer Status: predefined Contents: all integer numbers representable on a particular host computer, but at least numbers in the range –(231-1) .. 231-1 ECE 545 – Introduction to VHDL

  10. User defined integer types - Examples type day_of_month is range 0 to 31; type year is range 0 to 2100; type set_index_range is range 999 downto 100; constant number_of_bits: integer :=32; type bit_index is range 0 to number_of_bits-1; Values of bounds can be expressions, but need to be known when the model is analyzed. ECE 545 – Introduction to VHDL

  11. Enumeration Types ECE 545 – Introduction to VHDL

  12. Predefined enumeration types (1) boolean (true, false) bit (‘0’, ‘1’) characterVHDL-87: 128 7-bit ASCII characters VHDL-93: 256 ISO 8859 Latin-1 8-bit characters ECE 545 – Introduction to VHDL

  13. Predefined enumeration types (2) severity_level (note, warning, error, failure) Predefined in VHDL-93 only: file_open_kind (read_mode, write_mode, append_mode) file_open_status (open_ok, status_error, name_error, mode_error) ECE 545 – Introduction to VHDL

  14. User-defined enumeration types - Examples type state is (S0, S1); type alu_function is (disable, pass, add, subtract, multiply, divide); type octal_digit is (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’); type mixed is (lf, cr, ht, ‘-’, ‘/‘, ‘\’); Each value in an enumeration type must be either an identifier or a character literal ECE 545 – Introduction to VHDL

  15. Floating-Point Types ECE 545 – Introduction to VHDL

  16. Floating point types • Used to represent real numbers • Numbers are represented using a significand (mantissa) part and an exponent part • Conform to the IEEE standard 754 or 854 Minimum size of representation that must be supported by the implementation of the VHDL standard: VHDL-2001: 64-bit representation VHDL-87, VHDL-93: 32-bit representation ECE 545 – Introduction to VHDL

  17. Real literals - examples 23.1 23.1 46E5 46  105 1E+12 1  1012 1.234E09 1.234  109 34.0e-08 34.0  10-8 2#0.101#E5 0.1012  25 =(2-1+2-3)  25 8#0.4#E-6 0.48  8-6 = (4  8-1)  8-6 16#0.a5#E-8 0.a516  16-8 =(1016-1+516-2)  16-8 ECE 545 – Introduction to VHDL

  18. The ANSI/IEEE standard floating-point number representation formats ECE 545 – Introduction to VHDL

  19. User-defined floating-point types - Examples type input_level is range -10.0 to +10.0 type probability is range 0.0 to 1.0; constant max_output: real := 1.0E6; constant min_output: real := 1.0E-6; type output_range is max_output downto min_output; ECE 545 – Introduction to VHDL

  20. Attributes of Scalar Types ECE 545 – Introduction to VHDL

  21. Attributes of all scalar types T’left first (leftmost) value in T T’right last (rightmost) value in T T’low least value in T T’high greatest value in T Not available in VHDL-87: T’ascending true if T is an ascending range, false otherwise T’image(x) a string representing the value of x T’value(s) the value in T that is represented by s ECE 545 – Introduction to VHDL

  22. Attributes of all scalar types - examples type index_range is range 21 downto 11; index_range’left = 21 index_range’right = 11 index_range’low = 11 index_range’high = 21 index_range’ascending = false index_range’image(14) = “14” index_range’value(“20”) = 20 ECE 545 – Introduction to VHDL

  23. Attributes of discrete types T’pos(x) position number of x in T T’val(n) value in T at position n T’succ(x) value in T at position one greater than position of x T’pred(x) value in T at position one less than position of x T’leftof(x) value in T at position one to the left of x T’rightof(x) value in T at position one to the right of x ECE 545 – Introduction to VHDL

  24. Attributes of discrete types - examples type logic_level is (unknown, low, undriven, high); logic_level’pos(unknown) = 0 logic_level’val(3) = high logic_level’succ(unknown) = low logic_level’pred(undriven) = low logic_level’leftof(unknown) error logic_level’rightof(undriven) = high ECE 545 – Introduction to VHDL

  25. Subtypes ECE 545 – Introduction to VHDL

  26. Subtype • Defines a subset of a base type values • A condition that is used to determine which values are included in the subtype is called a constraint • All operations that are applicable to the base type also apply to any of its subtypes • Base type and subtype can be mixed in the operations, but the result must belong to the subtype, otherwise an error is generated. ECE 545 – Introduction to VHDL

  27. Predefined subtypes natural integers  0 positive integers > 0 Not predefined in VHDL-87: delay_length time  0 ECE 545 – Introduction to VHDL

  28. User-defined subtypes - Examples subtype bit_index is integer range 31 downto 0; subtype input_range is real range 1.0E-9 to 1.0E+12; ECE 545 – Introduction to VHDL

  29. Operators ECE 545 – Introduction to VHDL

  30. Operators (1) ECE 545 – Introduction to VHDL

  31. Operators (2) ECE 545 – Introduction to VHDL

  32. Operators (3) ECE 545 – Introduction to VHDL

  33. Operator Overloading ECE 545 – Introduction to VHDL

  34. Operator overloading • Operator overloading allows different argument types for a given operation (function) • The VHDL tools resolve which of these function to select based on the types of the inputs • This selection is transparent to the user as long as the function has been defined for the given argument types. ECE 545 – Introduction to VHDL

  35. Different declarations for the same operator - Example Declarations in the package ieee.std_logic_unsigned: function “+” ( L: std_logic_vector; R:std_logic_vector) return std_logic_vector; function “+” ( L: std_logic_vector; R: integer) return std_logic_vector; function “+” ( L: std_logic_vector; R:std_logic) return std_logic_vector; ECE 545 – Introduction to VHDL

  36. Different declarations for the same operator - Example signal count: std_logic_vector(7 downto 0); You can use: count <= count + “0000_0001”; or count <= count + 1; or count <= count + ‘1’; ECE 545 – Introduction to VHDL

  37. Specifying time in VHDL ECE 545 – Introduction to VHDL

  38. Physical data types Types representing physical quantities, such as time, voltage, capacitance, etc. are referred in VHDL as physical data types. TIME is the only predefined physical data type. Value of the physical data type is called a physical literal. ECE 545 – Introduction to VHDL

  39. Time values (physical literals) - Examples 7 ns 1 min min 10.65 us 10.65 fs Numeric value Space Unit of time (dimension) ECE 545 – Introduction to VHDL

  40. TIME values Numeric value can be an integer or a floating point number. Numeric value is optional. If not given, 1 is implied. Numeric value and dimension MUST be separated by a space. ECE 545 – Introduction to VHDL

  41. Units of time Unit Definition Base Unit fs femtoseconds (10-15 seconds) Derived Units ps picoseconds (10-12 seconds) ns nanoseconds (10-9 seconds) us microseconds (10-6 seconds) ms miliseconds (10-3 seconds) sec seconds min minutes (60 seconds) hr hours (3600 seconds) ECE 545 – Introduction to VHDL

  42. Values of the type TIME Value of a physical literal is defined in terms of integral multiples of the base unit, e.g. 10.65 us = 10,650,000,000 fs 10.65 fs = 10 fs Smallest available resolution in VHDL is 1 fs. Smallest available resolution in simulation can be set using a simulator command or parameter. ECE 545 – Introduction to VHDL

  43. Arithmetic operations on values of the type TIME Examples: 7 ns + 10 ns = 17 ns 1.2 ns – 12.6 ps = 1187400 fs 5 ns * 4.3 = 21.5 ns 20 ns / 5ns = 4 ECE 545 – Introduction to VHDL

  44. Propagation delay in VHDL ECE 545 – Introduction to VHDL

  45. Propagation delay in VHDL - Example entity MAJORITY is port (A_IN, B_IN, C_IN : in STD_LOGIC; Z_OUT : out STD_LOGIC); end MAJORITY; architecture DATA_FLOW of MAJORITY is begin Z_OUT <= (not A_IN and B_IN and C_IN) or (A_IN andnot B_IN and C_IN) or (A_IN and B_IN and not C_IN) or (A_IN and B_IN and C_IN) after 20 ns; end DATA_FLOW; ECE 545 – Introduction to VHDL

  46. Propagation delay - Example ECE 545 – Introduction to VHDL

  47. MLU: Block Diagram ECE 545 – Introduction to VHDL

  48. MLU - Architecture Body – Example 1 begin A1<=not A after 6 nswhen (NEG_A='1') else Aafter 5 ns; B1<=not B after 6 nswhen (NEG_B='1') else Bafter 5 ns; Y<=not Y1 after 6 nswhen (NEG_Y='1') else Y1after 5 ns; MUX_0<=A1 and B1after 3 ns; MUX_1<=A1 or B1after 3 ns; MUX_2<=A1 xor B1after 4 ns; MUX_3<=A1 xnor B1after 5 ns; L<=L1 & L0; with (L) select Y1<=MUX_0 after 7 nswhen "00", MUX_1 after 6 nswhen "01", MUX_2 after 8 nswhen "10", MUX_3 after 7 nswhen others; end MLU_DATAFLOW; ECE 545 – Introduction to VHDL

  49. MLU - Architecture Body – Example 2 begin A1<=not A after MUX2_delaywhen (NEG_A='1') else Aafter MUX_2_delay; B1<=not B after MUX2_delaywhen (NEG_B='1') else Bafter MUX2_delay; Y<=not Y1 after MUX2_delaywhen (NEG_Y='1') else Y1after MUX2_delay; MUX_0<=A1 and B1after GATE_delay; MUX_1<=A1 or B1after GATE_delay; MUX_2<=A1 xor B1after XOR_delay; MUX_3<=A1 xnor B1after XOR_delay; L<=L1 & L0; with (L) select Y1<=MUX_0 after MUX4_delaywhen "00", MUX_1 after MUX4_delaywhen "01", MUX_2 after MUX4_delaywhen "10", MUX_3 after MUX4_delaywhen others; end MLU_DATAFLOW; ECE 545 – Introduction to VHDL

  50. Delay constants constant MUX2_delay : time := 5 ns; constant GATE_delay : time := 3 ns; constant XOR_delay : time := 4 ns; constant MUX4_delay : time := 7 ns; Can be defined in the declarative portion of the architecture or in the package ECE 545 – Introduction to VHDL

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