Lecture 11 Switching & Forwarding

1. Lecture 11Switching & Forwarding EECS 122 University of California Berkeley

2. TOC: Switching & Forwarding • Why? • Switching Techniques • Switch Characteristics • Switch Examples • Switch Architectures • Summary Walrand

3. Switching: Why? • Direct vs. Switched Networks: • Direct Network Limitations: • Distance (coordination delay; propagation limitation) • Number of hosts (collisions; shared bandwidth; address tables) • Single link technology (cannot mix optical, wireless, …) • Internetworking: Externality gain at low cost n links Single link Switches Direct Switched Walrand

4. Switching: Techniques • Circuit-Switching (e.g., Telephone net.) • Packet-Switching • Datagram (e.g., IP, Ethernet) • Virtual Circuits (e.g., MPLS, ATM) • Source Routing • Comparison Walrand

5. Techniques: Circuit-Switching • Mechanism: Link divided into fixed, independent circuits (e.g., TDM, WDM) Circuit Switch Connection list Time scale: connection • Features: • Packets not switched independently (establish circuit before sending data) • Dedicated path and resources from source to destination • Setup time; low delays and guaranteed resources thereafter Walrand

6. Techniques: Packet-Switching • Mechanism: Whole link shared by all packets Packet Switch • Features: • Data separated into packets • Switching decision (output port) for each individual packet • Statistical multiplexing: Sum of peak rates may exceed link bandwidth (as long as mean does not) Walrand

7. Techniques: PS - Datagram • General idea: no connection establishment, but each packet contains enough info to specify destination • Switches contain forwarding tables (but no per-connection “state”) • Forwarding tables contain info on which outgoing port to use for each destination • Two types of addressing: • Layer 2 or Layer 3 Walrand

8. a 1b 1c 1d 2e 3f 4 a 1b 4c 3d 2e 2f 2 e|b| To From Datagram: Layer 2 (e.g., Ethernet) • Flat address space (no structure) • Forwarding table: Exact match of destination L2 address a d 1 2 2 1 4 e b 4 3 3 c f Walrand

9. 10100111 11010001 B 10100000 1101 Fixed Longest 11010000 A’ B’ D A Other 01000000 11010101 11100000 11001000 1100 11001101 C C’ 11001001 Datagram: Layer 3 (e.g., IP) E.g. 1 E.g. 2 • L3-network (e.g., IP) • Topological structure – match prefix • Either fixed prefix length or longest match E.g. 3 Walrand

10. 10100111 11010001 B 10100000 1101 Fixed Longest 11010000 A’ B’ D A Other 01000000 11010101 11100000 11001000 1100 11001101 C C’ 11001001 Datagram: Layer 3 (e.g., IP) E.g. 1 11011001 matches 4 bits at A, 1 at B, 3 at C  A = LPM 4 bits at A’  A’ = EM 11011001 Walrand

11. 10100111 11010001 B 10100000 1101 Fixed Longest 11010000 A’ B’ D A Other 01000000 11010101 11100000 11001000 1100 11001101 C C’ 11001001 Datagram: Layer 3 (e.g., IP) E.g. 2 11001001 matches 3 bits at A, 1 at B, 7 at C  C = LPM 11001001 Walrand

12. 10100111 11010001 B 10100000 1101 Fixed Longest 11010000 A’ B’ D A Other 01000000 11010101 11100000 11001000 1100 11001101 C C’ 11001001 Datagram: Layer 3 (e.g., IP) 01100101 matches 0 bit at A’  B’ 0 bit at B, 0 at C, 2 at D  D = LPM E.g. 3 01100101 Walrand

13. VC3 In, VC Out, VC 1, 1 4, 1 1, 2 4, 3 2, 1 4, 2 Techniques: PS – Virtual Circuit Connection setup establishes a path through switches • A virtual circuit ID (VCI) identifies path • Uses packet switching, with packets containing VCI • VCIs are often indices into per-switch connection tables; change at each hop VC1 1 4 1 4 VC1 VC2 VC2 VC1 2 3 3 2 VC1 VC2 VC1 …. Walrand

14. source 1 1 2 2 1 1 3 3 2 2 4 4 3 3 4 4 4 3 4 1 1 2 2 4 3 4 3 3 4 3 4 4 4 Techniques: Source Routing Each packet specifies the sequence of routers (or of output ports) from source to destination Walrand

15. Techniques: Comparison *The idea is that in case of failure, circuit and VC are lost; datagram routing can adapt after routing update …. Walrand

16. Switching: Characteristics • Ports • Fast Ethernet, OC-3, ATM, … • Protocols • ST, Link Agg., VLAN, OSPF, RIP, BGP, VPN, Load Balancing, WRED, WFQ • Performance • Throughput, Reliability, Power, … Walrand

17. Switching: Examples • Juniper M160 • Cisco “GSR” • Cisco “7600” • Cisco “catalyst 6500” • Extreme “Summit” • Foundry “ServerIron” Walrand

18. Examples: Cisco GSR - 12416 • WAN Router – Large throughput; SONET links • Up to 16 line cards at 10 Gbps each • Crossbar Fabric • Line Cards: 1-port OC-192c 4-port OC48c Many others (ATM, Ethernet, …) Cisco GSR 12416 19” 6ft 2ft Walrand

19. Examples: Juniper M160 • WAN Router – Large throughput; SONET links • Crossbar Fabric • Line Cards: 1-port OC-192c 4-port OC48c Many others (ATM, Ethernet, …) Juniper M160 19” Capacity: 80Gb/sPower: 2.6kW 3ft 2.5ft Walrand

20. Examples: Cisco 7600 • MAN-WAN Router • Up to 128 Gbps with Crossbar Fabric • 10Mbps – 10Gbps LAN Interfaces • OC-3 to OC-48 SONET Interfaces • MPLS, WFQ, LLQ, WRED, Traffic Shaping Walrand

21. Examples: Cisco cat 6500 • From LAN to Access • 48 to 576 10/100 Ethernet Interfaces • 10 GE, OC-3, OC-12, OC-48, ATM • QoS, ACL • Load Balancing; VPN • Up to 128Gbps (with crossbar) • L4-7 Switching • VLAN • IP Telephony (E1, T1, inline-power Ethernet) • SNMP, RMON Walrand

22. Examples: Extreme - Summit • 48 10/100 ports • 2 GE (SX, LX, or LX-70) • 17.5Gbps non-blocking • 10.1 Mpps • Wire speed L2 • Wire speed L3 static or RIP • OSPF, DVRMP, PIM, … Walrand

23. Examples: Foundry - ServerIron • Server Load Balancing • Transparent Cache Switching • Firewall Load Balancing • Global Server Load Balancing • Extended Layer 4-7 functionality including URL-, Cookie-, and SSL Session ID-based switching • Secure Network Address Translation (NAT) and Port address translation (PAT) Walrand

24. Switching: Architectures • Generic Architecture • First Generation • Second Generation • Third Generation • Input Functions • Output Functions • Interconnection Designs • OUT • IN • VOB • Combined IN/OUT Walrand

25. Architectures: Generic • Input and output interfaces are connected through an interconnect • A interconnect can be implemented by • Shared memory • low capacity routers (e.g., PC-based routers) • Shared bus • Medium capacity routers • Point-to-point (switched) bus • High capacity routers input interface output interface Inter- connect Walrand

26. Architectures: First Generation CPU Buffer Memory Route Table CPU Line Interface Line Interface Line Interface Memory MAC MAC MAC Shared Backplane Line Interface Typically < 0.5Gbps aggregate capacity Limited by rate of shared memory Slide by Nick McKeown Walrand

27. Architectures: Second Generation CPU Buffer Memory Route Table Line Card Line Card Line Card Buffer Memory Buffer Memory Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC MAC MAC Typically < 5Gb/s aggregate capacity Limited by shared bus Slide by Nick McKeown Walrand

28. Architectures: Third Generation Switched Backplane Line Card CPU Card Line Card Local Buffer Memory Local Buffer Memory Line Interface CPU Routing Table Memory Fwding Table Fwding Table MAC MAC Typically < 50Gbps aggregate capacity Slide by Nick McKeown Walrand

29. Architectures: Input Functions • Packet forwarding: decide to which output interface to forward each packet based on the information in packet header • examine packet header • lookup in forwarding table • update packet header Walrand

30. Architectures: Output Functions • Buffer management: decide when and which packet to drop • Scheduler: decide when and which packet to transmit Buffer Scheduler 1 2 Walrand

31. flow 1 Classifier flow 2 Scheduler 1 2 flow n Buffer management Architectures: Output Functions (ct) • Packet classification: map each packet to a predefined flow/connection (for datagram forwarding) • use to implement more sophisticated services (e.g., QoS) • Flow: a subset of packets between any two endpoints in the network Walrand

32. input interface output interface Backplane RO C Architectures: Output Queued • Only output interfaces store packets • Advantage • Easy to design algorithms: only one congestion point • Disadvantage • Requires an output speedup Ro/C = N, where N is the number of interfaces  not feasible for large N Walrand

33. input interface output interface Backplane RO C Architectures: Input Queues • Only input interfaces store packets • Advantages • Easy to build • Simple algorithms • Disadvantages • HOL Blocking • In practice:Speedup of 2 suffices Walrand

34. Note: Head-of-line Blocking • The cell at the head of an input queue cannot be transferred, thus blocking the following cells Cannot be transferred because of HOL blocking Cannot be transferred because of output contention Input 1 Output 1 Input 2 Output 2 Input 3 Output 3 Being transferred Walrand

35. Architectures: Virtual Output Buffers • OUT buffers at each input port • Complexity: Matching Problem • Full throughput algorithm • Good Heuristic Crossbar Note: Figure from Prof. Varaiya’s notes for EE228b Walrand

36. VOB: Full Throughput • Maximum Weighted Matching: A = 14 B = 11 C = 15 D = 10 B + C > A + D => Serve (B, C) Walrand

37. VOB: Good Heuristic – i-SLIP • Inputs request permission to send from outputs • Outputs grant permissions to inputs (round-robin) • Inputs accept permissions (round-robin) Request Grant Accept Iter 2 3 1 1 3 2 Last Accept Last Grant Walrand

38. input interface output interface Backplane RO C Architectures: Combined IN/OUT • Both input and output interfaces store packets • Advantages • Easy to built • Utilization 1 can be achieved with limited input/output speedup (<= 2) • Disadvantages • Harder to design algorithms • Two congestion points • Need to design flow control Walrand

39. Switching: Summary • Switching needed for big networks • Internetworking externality • Circuit • Packet – VC: QoS possible • Packet – Datagram • L2: Limited by flat address space • L3: • Exact Match: Easy lookup – less efficient • Longest Prefix Match • Switch functions: control and data • Different Architectures: • cost vs. performance Walrand