ECE 4110– Sequential Logic Design

ECE 4110– Sequential Logic Design Lecture #31 • Agenda • von Neumann Stored Program Computer Architecture • Announcements 1. Friday: Thanksgiving Holiday, No classes.

von Neumann Computer • CPU 1) Control Unit2) Processing Unit3) Control Signals4) Test Signals

von Neumann Computer • Register Loads- each register in the processing unit can be loaded by the control unit- the input to most registers is Bus2- the CCR input is the ALU- the loads are synchronous to clock and occur on the following state- we can make a register in RTL as follows:MAR_Register : process (Clock, Reset) begin if (Reset = '0') then MAR <= "0000"; elsif (Clock'event and Clock='1') then if (MAR_Load = '1') then MAR <= Bus2; end if; end if; end process;

von Neumann Computer • Control Signals- the Bus1 and Bus2 control lines come from the control unit and drive the multiplexers- the WRITE line is a synchronous load to memory from Memory_Out- CCR_Load will load the status bits (NZVC), whose values depend on the previous ALU operation- the ALU_Sel line tells the ALU which function to perform (AND, ADD, …) • Test Signals- the Instruction Register (IR) holds the Opcode for the Control Unit to base state decisions on- the CCR_Result is the NZVC status bits from an ALU operation and influence state decisions

von Neumann Computer • Instruction ExecutionState 0- put the current Program Counter value on the Memory Address Bus to read the first Opcode RTL: MAR <= PC Control: Bus1_Sel = PC Bus2_Sel = Bus1 MAR_LoadState 1- bring in the contents of memory (the Opcode) and put into the IR- increment PC to point at either the Operand or next Opcode in memory RTL: IR <= Memory_Out PC = PC + 1 Control: Bus2_Sel = Memory_Out IR_Load PC_Inc

von Neumann Computer • Instruction ExecutionState 2- the Control Unit now decodes IR- this dictates the next state and which control signals are asserted (IR = ADD_XY) (IR = LDX_IMM) RTL: Z <= X RTL: MAR <= PC Control: Bus1_Sel = X Control: Bus1_Sel = PC Bus2_Sel = Bus1 Bus2_Sel = Bus1Z_LoadMAR_LoadState 3 RTL: ALU = ADD RTL: X <= Memory_Out Control: Bus1_Sel = Y Control: Bus2_Sel = Memory_Out Bus2_Sel = ALU X_LoadALU_Sel = ADD PC_IncX_LoadCCR_Load

Control Unit Sub-Operations • Fetch • Get next instruction into IR • PC: program counter, always points to next instruction • IR: holds the fetched instruction Processor Control unit Datapath ALU Controller Control /Status Registers Y PC IR 100 MAR X load X, I/O 100 load X, 101 123 102 ADD X, Y Store X,

Control Unit Sub-Operations • Decode • Determine what the instruction means Processor Control unit Datapath ALU Controller Control /Status Registers 4 Y PC IR 100 MAR X load X, I/O Memory 100 load X, 101 123 102 ADD X,Y

Control Unit Sub-Operations • Fetch operands • Move data from memory to data-path register Processor Control unit Datapath ALU Controller Control /Status Registers 4 Y 101 123 PC IR 100 X MAR load X, I/O Memory 100 load X, 101 123 102 ADD X,Y

Control Unit Sub-Operations • Execute • Move data through the ALU • This particular instruction does nothing during this sub-operation Processor Control unit Datapath ALU Controller Control /Status Registers 4 Y 123 PC IR 100 MAR X load X, I/O Memory 100 load X, 101 123 102 ADD X,Y

Control Unit Sub-Operations • Store results • Write data from register to memory • This particular instruction does nothing during this sub-operation Processor Control unit Datapath ALU Controller Control /Status Registers 4 Y 123 PC IR 100 MAR X load X, I/O Memory 100 load X, 101 123 102 ADD X,Y

Processor Control unit Datapath ALU Controller Control /Status Registers Y PC IR X MAR I/O Memory 100 load X, 101 123 102 ADD X,Y Control Unit Sub-Operations PC=100 4 123 100

Processor Control unit Datapath ALU Controller Control /Status Registers Y PC IR X MAR I/O Memory 100 load X, 101 123 102 ADD X,Y Instruction Cycles PC=100 PC=101 4 123 101

Processor Control unit Datapath ALU Controller Control /Status Registers Y PC IR X MAR I/O Memory 100 load X, 101 123 102 ADD X,Y Instruction Cycles PC=100 PC=101 4 127 101 PC=102

ECE 4110– Sequential Logic Design