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Instruction Set & Assembly Language Programming

Instruction Set & Assembly Language Programming. Jianjian SONG Software Institute, Nanjing University. Content. Computer Architecture Taxonomy ARM Architecture Introduction ARM Instruction Set ARM Assembly Language Programming. 1. Computer Architecture Taxonomy. What is architecture?.

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Instruction Set & Assembly Language Programming

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  1. Instruction Set & Assembly Language Programming Jianjian SONG Software Institute, Nanjing University

  2. Content • Computer Architecture Taxonomy • ARM Architecture Introduction • ARM Instruction Set • ARM Assembly Language Programming

  3. 1. Computer Architecture Taxonomy • What is architecture?

  4. Architecture & Organization 1 • Architecture is those attributes visible to the programmer • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. • e.g. Is there a multiply instruction? • Organization is how features are implemented • Control signals, interfaces, memory technology. • e.g. Is there a hardware multiply unit or is it done by repeated addition?

  5. Architecture & Organization 2 • All Intel x86 family share the same basic architecture • The IBM System/370 family share the same basic architecture • This gives code compatibility • At least backwards • Organization differs between different versions

  6. von Neumann architecture • Memory holds data, instructions. • Central processing unit (CPU) fetches instructions from memory. • Separate CPU and memory distinguishes programmable computer. • CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.

  7. CPU + memory memory address CPU PC 200 data ADD r5,r1,r3 ADD r5,r1,r3 IR 200

  8. Harvard architecture address CPU data memory PC data address program memory data

  9. von Neumann vs. Harvard • Harvard can’t use self-modifying code. • Harvard allows two simultaneous memory fetches. • Most DSPs use Harvard architecture for streaming data: • greater memory bandwidth; • more predictable bandwidth.

  10. RISC vs. CISC • Complex instruction set computer (CISC): • many addressing modes; • many operations. • Reduced instruction set computer (RISC): • load/store; • pipelinable instructions.

  11. Load-store Architecture • 指令集仅能处理(如ADD、SUB等)寄存器中(或指令中直接指定)的值，而且总是将处理结果放回寄存器中。针对存储器的唯一操作是将存储器的值装入寄存器(load指令)，或将寄存器的值存到存储器(store指令)。 • 相比较，典型的CISC处理器允许将存储器中的值加(ADD)到寄存器，有时还允许将寄存器的值加(ADD)到存储器中。

  12. Instruction set characteristics • Fixed vs. variable length. • Addressing modes. • Number of operands. • Types of operands.

  13. Programming model • Programming model: registers visible to the programmer. • Some registers are not visible (e.g. IR).

  14. Multiple implementations • Successful architectures have several implementations: • varying clock speeds; • different bus widths; • different cache sizes; • etc.

  15. 2. ARM Architecture Introduction • ARM (Advanced RISC Machines) • ARM公司是一家设计公司，是IP 供应商，靠转让设计许可证由合作伙伴生产各具特色的芯片。 • What is IP？Intellectual Property

  16. ARM的特点 • ARM具有RISC体系的一般特点： • 大量寄存器 • 绝大多数操作都在寄存器中进行，通过Load/Store的在内存和寄存器间传递数据。 • 寻址方式简单 • 采用固定长度的指令格式 • 此外， • 小体积、低功耗、低成本、高性能 • 16位/32位双指令集 • 全球众多合作伙伴

  17. ARM体系结构的版本和扩充 • 六个版本 • ARMv1 ~ ARMv6 • ARM体系结构的扩充 • Thumb (Tvariant): 16位指令集，用以改善指令密度； • DSP (Evariant): 用于DSP应用的算术运算指令集； • Jazeller (J variant): 允许直接执行Java字节码 什么是指令密度？ 执行同等操作序列的前提下，单位内存空间所容纳的机器指令数。

  18. ARM体系结构版本的命名格式 • 命名字符串: • ARM • vx (x: 指令集版本号，1~6) • 表示变种的字符 (如 T, E, J ) • 用字符x表示排除某种写功能。

  19. ARM处理器系列 • ARM7系列 • ARM9系列 • ARM9E系列 • ARM10系列 • SecureCore系列 • Intel StrongARM • Intel XScale

  20. 3. ARM Instruction Set • ARM assembly language • ARM programming model • ARM memory organization • ARM data operations • ARM flow of control

  21. Assembly language • Why assembly language? • One-to-one with instructions (more or less). • Basic features: • One instruction per line. • Labels provide names for addresses (usually in first column). • Instructions often start in later columns. • Columns run to end of line.

  22. ARM assembly language example label1 ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment

  23. 31 28 27 26 25 24 21 20 19 16 15 12 11 0 cond 00 X opcode S Rn Rd Shifter-operand ARM指令的一般编码格式 opcode: 指令操作符编码 cond: 指令执行条件编码 S: 指令的操作是否影响CPSR的值 Rn: 包含第一个操作数的寄存器编码 Rd: 目标寄存器编码 Shifter_operand: 第二个操作数

  24. ARM指令的基本寻址方式 • 寄存器寻址 • 例：ADD R0 , R1 , R2 ; (R1)+(R2)→R0 • 立即数寻址 • 例：ADD R3 , R3 , #2 ; (R3)+2→R3 • 寄存器间接寻址 • 例：LDR R0 , [R3] ; ((R3))→R0 • 寄存器变址 • 例：LDR R0 , [R1, #4] ; ((R1)+4)→R0 • 相对寻址 • 例：B rel ; (PC)+rel→PC

  25. Pseudo-ops • Some assembler directives don’t correspond directly to instructions: • Define current address. • Reserve storage. • Constants.

  26. N Z C V ARM programming model r0 r8 r1 r9 0 31 r2 r10 CPSR r3 r11 r4 r12 r5 r13 r6 r14 r7 r15 (PC)

  27. Endianness • Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian

  28. ARM data types • Word is 32 bits long. • Word can be divided into four 8-bit bytes. • ARM addresses can be 32 bits long. • Address refers to byte. • Address 4 starts at byte 4. • Can be configured at power-up as either little- or big-endian mode.

  29. ARM status bits • Every arithmetic, logical, or shifting operation sets CPSR bits: • N (negative), Z (zero), C (carry), V (overflow). • Examples: • -1 + 1 = 0: NZCV = 0110. • 231-1+1 = -231: NZCV = 0101.

  30. Instructions Overview • Data instructions • Move Instructions • Load/Store instructions • Comparison instructions • Branch instructions

  31. ARM data instructions • Basic format: ADD r0,r1,r2 • Computes r1+r2, stores in r0. • Immediate operand: ADD r0,r1,#2 • Computes r1+2, stores in r0.

  32. ADD, ADC : add (w. carry) SUB, SBC : subtract (w. carry) RSB, RSC : reverse subtract (w. carry) MUL, MLA : multiply (and accumulate) AND, ORR, EOR BIC : bit clear LSL, LSR : logical shift left/right ASL, ASR : arithmetic shift left/right ROR : rotate right RRX : rotate right extended with C ARM data instructions

  33. Data operation varieties • Logical shift: • fills with zeroes. • Arithmetic shift: • fills with ones. • RRX performs 33-bit rotate, including C bit from CPSR above sign bit.

  34. ARM move instructions • MOV, MVN : move (negated) MOV r0, r1 ; sets r0 to r1

  35. ARM load/store instructions • LDR, LDRH, LDRB : load (half-word, byte) • STR, STRH, STRB : store (half-word, byte) • Addressing modes: • register indirect : LDR r0,[r1] • with second register : LDR r0,[r1,-r2] • with constant : LDR r0,[r1,#4]

  36. ARM comparison instructions • CMP : compare • CMN : negated compare • TST : bit-wise test • TEQ : bit-wise negated test • These instructions set only the NZCV bits of CPSR.

  37. ARM branch instructions • B: Branch • BL: Branch and Link

  38. ARM ADR pseudo-op • Cannot refer to an address directly in an instruction. • Generate value by performing arithmetic on PC. • ADR pseudo-op generates instruction required to calculate address: ADR r1,FOO

  39. Example: C assignments • C: x = (a + b) - c; • Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b, reusing r4 LDR r1,[r4] ; get value of b ADD r3,r0,r1 ; compute a+b ADR r4,c ; get address for c LDR r2,[r4] ; get value of c

  40. C assignment, cont’d. SUB r3,r3,r2 ; complete computation of x ADR r4,x ; get address for x STR r3,[r4] ; store value of x

  41. Example: C assignment • C: y = a*(b+c); • Assembler: ADR r4,b ; get address for b LDR r0,[r4] ; get value of b ADR r4,c ; get address for c LDR r1,[r4] ; get value of c ADD r2,r0,r1 ; compute partial result ADR r4,a ; get address for a LDR r0,[r4] ; get value of a

  42. C assignment, cont’d. MUL r2,r2,r0 ; compute final value for y ADR r4,y ; get address for y STR r2,[r4] ; store y

  43. Example: C assignment • C: z = (a << 2) | (b & 15); • Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a MOV r0,r0,LSL 2 ; perform shift ADR r4,b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR

  44. C assignment, cont’d. ADR r4,z ; get address for z STR r1,[r4] ; store value for z

  45. Additional addressing modes • Base-plus-offset addressing: LDR r0,[r1,#16] • Loads from location r1+16 • Auto-indexing increments base register: LDR r0,[r1,#16]! • Post-indexing fetches, then does offset: LDR r0,[r1],#16 • Loads r0 from r1, then adds 16 to r1.

  46. ARM flow of control • All operations can be performed conditionally, testing CPSR: • EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE • Branch operation: B #100 • Can be performed conditionally.

  47. Example: if statement • C: if (a < b) { x = 5; y = c + d; } else x = c - d; • Assembler: ; compute and test condition ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b LDR r1,[r4] ; get value for b CMP r0,r1 ; compare a < b BGE fblock ; if a >= b, branch to false block

  48. If statement, cont’d. ; true block MOV r0,#5 ; generate value for x ADR r4,x ; get address for x STR r0,[r4] ; store x ADR r4,c ; get address for c LDR r0,[r4] ; get value of c ADR r4,d ; get address for d LDR r1,[r4] ; get value of d ADD r0,r0,r1 ; compute y ADR r4,y ; get address for y STR r0,[r4] ; store y B after ; branch around false block

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