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Implementation of Paging in uCOS-II

Implementation of Paging in uCOS-II. 20100422 Ke, Dian Chia. Outline. uCOS-II Application Model x86 Operating Mode x86 Interrupt Disk I/O Testing Result Q & A Appendix. uCOS-II Application Model (1 / 2). OS_STK TaskStk[N_TASKS][STK_SIZE]; … main(){ … OSInit(); …

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Implementation of Paging in uCOS-II

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  1. Implementation of Paging in uCOS-II 20100422 Ke, Dian Chia

  2. Outline • uCOS-II Application Model • x86 Operating Mode • x86 Interrupt • Disk I/O • Testing Result • Q & A • Appendix

  3. uCOS-II Application Model (1 / 2) OS_STK TaskStk[N_TASKS][STK_SIZE]; … main(){ … OSInit(); … OSTaskCreate(task, (void *)0, &TaskStk[0][STK_SIZE - 1], 0); OSStart(); } task(){ … } OS_TCB OSTCBTbl[] in os_core.c OSTCBFreeList OS_InitTCBList(); OS_MemInit(); … OSTCBPrio OSTCBStkPtr

  4. uCOS-II Application Model (2 / 2) tick ISR and rate set main starts main ends tick tick tick other tasks ready 1 10 ……….. … … … TaskStart ready TaskStart starts

  5. x86 Operating Mode (1 / 11) • real mode • All start up in real mode at power-on; 80186 and earlier had only real mode. • protected mode • The foundation for all subsequent enhancements to the x86 architecture. • virtual 8086 mode • 80386 and later, virtual real mode, V86-mode or VM86 is whereby the CPU (in protected mode) is running an “emulated" 16bit “segmented” model (real mode) machine.

  6. x86 Operating Mode (2 / 11) • unreal mode • unreal mode, big real mode, huge real mode, or flat real mode, is a variant of real mode in which one or more data segment registers have been loaded with 32-bit addresses and limits. • system management mode • First released with 386SL, a mode in which all normal execution (including OS) is suspended, and special separate software (firmware or hardware-assisted debugger) is executed in high-privilege mode. • long mode • x86-64

  7. x86 Operating Mode (3 / 11)real mode • 20 bit segmented memory address space, 220 = 1 MB of addressable memory • direct software access to BIOS routines and peripheral hardware • no memory protection, multi-tasking or code privilege levels • A20 line • Gate-A20 of IBM Personal Computer AT

  8. x86 Operating Mode (4 / 11)real mode

  9. x86 Operating Mode (5 / 11)protected mode • virtual memory, paging, multi-tasking, … • first released with 80286 • 16-bit offset, 64KB segments • 24-bit address bus, 16MB • only resetting to enter real mode • extended with 80386 • 32-bit offset, 4GB segments • 32-bit address bus, 4GB • security and stability

  10. x86 Operating Mode (6 / 11)protected mode • entering • GDT created with a minimum of three entries: null, code and data segment descriptor • load GDT • disable interrupt • 21st address line (A20) enabled • ; set PE bitmov eax, cr0or eax, 1mov cr0, eax • ; far jump (cs = selector of code segment)jmp cs:@pm@pm: ; Now we are in PM. • exiting • loading segment registers with real mode values, disabling A20 line, clearing PE bit in the CR0 register

  11. x86 Operating Mode (7 / 11)protected mode • privilege levels

  12. x86 Operating Mode (8 / 11)protected mode • segment addressing

  13. x86 Operating Mode (9 / 11)protected mode • segment descriptor entry

  14. x86 Operating Mode (10 / 11)unreal mode Too big object Where to put ? 64 K CS

  15. x86 Operating Mode (11 / 11)unreal mode cli ; interrupts off push ds ; save segment lgdt [gdtinfo] ; load gdt mov eax, cr0 ; switch to pmode by or al, 1 ; set pmode bit mov cr0, eax mov bx, 0x08 ; some descriptor mov ds, bx ; cache set and al, 0xFE ; back to real mode mov cr0, eax ; by toggling bit again pop ds ; get back old segment sti ; interrupts on mov bx, 0x0f01 ; attrib/char of smiley mov eax, 0x0b8000 ; note 32 bit offset mov word [ds: eax], bx 8 Bytes cached

  16. x86 Interrupt (1 / 4) PR resolves which interrupt request has the highest priority. IRR saves information about all interrupt requests to be serviced. IMR stores the information which interrupt request to be masked. ISR stores information about interrupts that are being serviced.

  17. x86 Interrupt (2 / 4) system timer keyboard serial port 2 or 4 serial port 1 or 3 LPT port 2 or sound card floppy disk controller LPT port 1 or sound card real-time clock PS/2 connector mouse primary ATA channel secondary ATA channel

  18. x86 Interrupt (3 / 4)

  19. x86 Interrupt (4 / 4)

  20. Disk I/O (1 / 2) Port Read/Write Misc ----- -------------- ------------------------------------------------- 1f0 r/w data register, the bytes are written/read here 1f1 r error register (look these values up yourself) 1f2 r/w sector count, how many sectors to read/write 1f3 r/w sector number, the actual sector wanted 1f4 r/w cylinder low, cylinders is 0-1024 1f5 r/w cylinder high, this makes up the rest of the 1024 1f6 r/w drive/head bit 7 = 1 bit 6 = 0 bit 5 = 1 bit 4 = 0 drive 0 select = 1 drive 1 select bit 3-0 head select bits

  21. Port Read/Write Misc ----- -------------- ------------------------------------------------- 1f7 r status register bit 7 = 1 controller is executing a command bit 6 = 1 drive is ready bit 5 = 1 write fault bit 4 = 1 seek complete bit 3 = 1 sector buffer requires servicing bit 2 = 1 disk data read corrected bit 1 = 1 index - set to 1 each revolution bit 0 = 1 previous command ended in an error 1f7 w command register 50h format track 20h read sectors with retry 21h read sectors without retry 22h read long with retry 23h read long without retry 30h write sectors with retry 31h write sectors without retry 32h write long with retry 33h write long without retry

  22. Testing Result (1 / 3)

  23. Testing Result (2 / 3)

  24. Testing Result (3 / 3)

  25. Q & A

  26. hardware RESET BIOS POST… boot device chosen, copy MBR (512 Bytes, stage 1 LILO) into memory 0x7c00 (also check /arch/i386/boot/bootsect.S) AppendixLinux Booting Involved (1 / 5) 0xffff0000 + 0xfff0 = 0xfffffff0 (BIOS, mapped by hardware into RAM)

  27. AppendixLinux Booting Involved (2 / 5) • cs: ip = 0x7c0: 0x0 = 0x7c00 • ss = es = ds = cs, sp = 0x7c00 decompressed kernel 0x100000 (1 M) 0x98000 stage 2 LILO 0x96c00 jump 512 Bytes 0x96a00 0x969ff real mode stack 0x90200 First 512 Bytes of kernel 0x90000 move MBR 512 Bytes 0x7c00

  28. AppendixLinux Booting Involved (3 / 5) • setup() (/arch/i386/boot/setup.S) • reinitialize all hardware • set A20 line • switch to protected mode with a temp GDT • cs = 0x9020  cs = a 4G code segment

  29. AppendixLinux Booting Involved (4 / 5) • startup_32() (start of compressed image, /arch/i386/boot/compressed/head.S) • decompress kernel to 0x100000 • ljmp $(__BOOT_CS), $0x100000

  30. AppendixLinux Booting Involved (5 / 5) • startup32() (uncompressed, /arch/i386/kernel/head.S) • initialize segment reg. • fill bss segment of kernel with zeros • set page directory into cr3, enable paging • lgdt and lidt with the final GDT

  31. AppendixA Simple Segmentation Sample (1 / 3)

  32. AppendixA Simple Segmentation Sample (2 / 3) ecx = original esp + 4 original esp original esp ebp esp original ebp esp ecx 8 20 j = 0 points to 12 esp k = &j

  33. AppendixA Simple Segmentation Sample (3 / 3)

  34. AppendixProcess Address Space (1 / 6)

  35. AppendixProcess Address Space (2 / 6) pgd pgd_t *

  36. AppendixProcess Address Space (3 / 6)

  37. AppendixProcess Address Space (4 / 6)

  38. AppendixProcess Address Space (5 / 6) 0xbf819000 0xbf8180e0 stack 0xbf804000 0xb8019000 mmap 0xb8018000 0xb8017000 0x80e3000 bss 0x80c1000 0x80bf000 0x80bec20 data 0x80be484 0x80be000 0x80bd482 text 0x8048000

  39. AppendixProcess Address Space (6 / 6)

  40. gloInitData Dir Table Offset 0x80be46c 0x80be46c = 00001000000010111110010001101100 __USER_DS, 0x7b 0x1def0000 0x1def046c 0x2fe4b000 0x1def0067 0 0x2fe4b067 pte at 0xefe4b2f8 CR3 0xeff3a000 pgd at 0xeff3a080 content in 0x1def046c is 0x1e

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