Lab13: FPGA Circuit Realization COE0501 Dr. Steve Jacobs Yee-Wing Hsieh

1. Lab13: FPGA Circuit RealizationCOE0501Dr. Steve JacobsYee-Wing Hsieh

2. Design Process Design process:(Labs 1-7) 1. Design entry (on paper) 2. Device mapping (TTL components) 3. Synthesis (proto-board) 4. Testing (logic analyzer) Design process:(Labs 9-12) 1. Design entry (schematics capture) 2. Device mapping (TTL components) 3. Testing (test vector simulation) 4. Synthesis (proto-board) 5. Testing (logic analyzer)

3. Improving Design Process Prototyping on Proto-board 1. Time consuming 2. Discrete TTL components (costly) 3. Wiring errors Programmable Devices (e.g. FPGA) 1. Fast prototyping 2. Highly integrated (less costly) 3. Good performance (speed/functionality)

4. Combinational Logic Gates 1. ROM (hardwire at mask level) 2. PROM (program once) 3. EPROM (UV erasable) 4. EEPROM (electrically erasable) 5. PAL/PLA/GAL (array of ANDs/ORs)

5. Field Programmable Gate Array Three Components: 1. Complex Logic Blocks (CLBs) 2. I/O Blocks 3. Interconnects Two Categories: 1. fine grain - a sea of gates/transistors 2. coarse grain - macro cells consist of flip flops and look up table (LUT)

6. FPGA Components

7. Complex Logic Blocks (CLBs)

8. Complex Logic Blocks (CLBs)

9. Complex Logic Blocks (CLBs)

10. I/O Blocks

11. Programmable Interconnects

12. Configuring FPGAs • Switches/Multiplexors determine the functionality • of CLBs, I/O blocks and interconnects. • Memory devices control the settings of switches/multiplexors • Configure FPGA by storing appropriate ‘1’s and ‘0’s to the • memory devices! • Problem: 1. Difficult to configure thousands/millions • of switch/multiplexor settings manually. • 2. Difficult to bind (map) logic functions • to PLD resources • Solution: Use software packages to perform binding and • configure FPGA automatically.

13. Design Capture 1. Logic (boolean expressions) 2. Schematic capture » 3. Hardware Description Language (e.g., VHDL/Verilog)

14. Designing with VHDL Design Process: (lab 13) 1. Design entry (VHDL) 2. Testing (VHDL test vector simulation) 3. Synthesis (FPGA, standard cell, full custom) 4. Testing (logic analyzer)