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Investigating Predictive Techniques for Out of Order Logic

Explore applying memoization and predictive techniques to reduce power consumption in complex out-of-order logic designs optimized for performance. Examining key structures and redesigning logical components to introduce power savings while ensuring efficient recovery from mispredictions.

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Investigating Predictive Techniques for Out of Order Logic

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  1. Investigating Predictive Techniques for Out of Order Logic Kenneth Barr Kenneth Conley Serhii Zhak

  2. The Problem • Out of order logic is getting more complex, increasing power consumption. • Optimized for performance, not power • How can memoization and predictive techniques be applied to introduce power savings?

  3. Methodology • Examine key out of order logic structures: • Register renaming • Superscalar issue logic • Look for correlation between state and asserted control signals • Redesign logical structures to increase correlation • Add new logical structures to apply predictive techniques to out of order logic

  4. Issues • How do we determine the power savings of our scheme? • How do we detect mispredictions, and what kind of mispredictions are possible? • How do we recover from mispredictions in the issue logic?

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