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WinCupl

WinCupl. Module M2.2 Section 4.2. 2. 19. X. !(X $ Y). 18. 3. X $ Y. Y. 17. !(X # Y). 16. X # Y. 15. !(X & Y). 14. X & Y. 13. !Y. 12. !X. GAL 16V8. Experiment 2. CUPL Header. CUPL Comments. CUPL Inputs and Outputs. CUPL Logic Equations. Running WinCupl.

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WinCupl

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  1. WinCupl Module M2.2 Section 4.2

  2. 2 19 X !(X $ Y) 18 3 X $ Y Y 17 !(X # Y) 16 X # Y 15 !(X & Y) 14 X & Y 13 !Y 12 !X GAL 16V8 Experiment 2

  3. CUPL Header

  4. CUPL Comments

  5. CUPL Inputs and Outputs

  6. CUPL Logic Equations

  7. Running WinCupl

  8. CUPL Chip Diagramin .DOC File

  9. JEDEC File

  10. JEDEC File Header

  11. JEDEC File Fuse Map

  12. Simulator • Copy Exp2.pld to Exp2.si • Delete everything after the header • Add ORDER statement • Add test VECTORS

  13. Copy this header EXACTLY from the file exp2.pld and copy to the file exp2.si

  14. ORDER statement Test vectors Add the following to the file exp2.si

  15. Outputs: L, H Inputs: 0, 1 ORDER Statement 01 HLLHHLHL Test Vector %2 means “leave 2 spaces when printing simulation results”

  16. The 4 test vectors represent the 4 rows in the truth table. Test Vectors

  17. WinCupl Demo

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