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Hardware Implementation of a Signaling Protocol

Hardware Implementation of a Signaling Protocol. Haobo Wang Malathi Veeraraghavan Ramesh Karri. Center for Advanced Technology in Telecommunications. Polytechnic University. Outline. Background and problem statement Hardware signaling – Why and how?

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Hardware Implementation of a Signaling Protocol

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  1. Hardware Implementation of a Signaling Protocol Haobo Wang Malathi Veeraraghavan Ramesh Karri Center for Advanced Technology in Telecommunications Polytechnic University

  2. Outline • Background and problem statement • Hardware signaling – Why and how? • A signaling protocol and its hardware implementation • Messages, data tables, procedures… • Hardware platform, state transition diagram… • Conclusion and future work

  3. Background and problem statement • What is a signaling protocol? • Set up and tear down connections in connection-oriented networks • Signaling protocols are primarily implemented in software • Two reasons: Complexity and flexibility • Cost: Performance • Problem statement of this work • Implement signaling protocol in reconfigurable hardware

  4. Why hardware signaling • Low call setup delay - 4 us per switch • Fast restoration • High throughput – 150,000 calls/sec • Support large scaled core switches – TCP switching

  5. Challenges of hardware signaling • For a hardware-oriented signaling protocol • Maintain per connection state • Many data table manipulations • Lots of messages, parameters, procedures • Resource management • For CR-LDP • TLV

  6. Our approach to hardware signaling • Partition signaling functions • Hardware: common and simple functions • Software: infrequent and complex functions • Use reconfigurable hardware – FPGA to solve the problem of flexibility

  7. IP 4.8.2.1 IP 7.4.1.4 IP 7.4.1.2 IP 5.7.2.1 IP 5.7.2.3 Network and node view

  8. We defined four messages Setup Setup Success Release Release Confirm

  9. And five tables Routing table CAC table Connectivity table State table Switch mapping table

  10. Processing of Setup message Connectivity table IP 5.7.2.1 IP 7.4.1.4 IP 4.8.2.1 Int.#1 Int.#3 IP 5.7.2.3 IP 7.4.1.2 Int.#10 Int.#5 State table Routing table Switch mapping table CAC table

  11. Hardware platform – Wildforce

  12. State transition diagram of signaling hardware accelerator

  13. Write back marked as used Timeslot manager Interface number … 15 14 13 12 3 2 1 0 0 1 … 2 Priority Decoder 3 … … 60 61 … Output timeslot 62 63 … … Scratch register

  14. Simulation result for Setup message Simulation result for Release message Simulation result for Setup Success message Simulation result for Release Confirm message The simulation results

  15. Assuming a 25 MHz clock Total setup and teardown time: 5.9 to 6.8 us Call handling capacity of 150,000 calls/sec …more words * Based on a worst-case search through a four option routing table

  16. Conclusion and future work • Feasibility • Yes, hardware signaling is possible if we implement the common and simple operations in hardware and infrequent and complex operations in software • Advantage • 100x-1000x speedup vis-à-vis software implementations • Future work • GMPLS, applications

  17. Thank your all! Please visit our website for more details, http://eeweb1.poly.edu/networks/html-files/hw_sig.htm

  18. Any questions?

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