Various SoC-Related Applications, Business Models, Global Industries & CareerLife Planning

1. Various SoC-Related Applications, Business Models, Global Industries & CareerLife Planning

2. Four Major Technology Drivers • RF and AMS • SoC • MPU • (Embedded) Memory

3. RF and AMS (Analog/Mixed Signal)

4. Application Spectrum of Various Competing RF Technologies Cost is one of the key factors determining the location of boundaries between the kinds of RF semiconductors (e.g., Si, SiGe, GaAs, and InP)

5. 1. Boundary between the group IV semiconductors Si and SiGe and the III-V semiconductor GaAs has been moving to higher frequencies with time. 2. Eventually, metamorphic high electron mobility transistors (MHEMTs) may displace both GaAs pseudomorphic high electron mobility transistors (PHEMTs) and InP high electron mobility transistors (HEMTs). 3. The wide bandgap semiconductors such as SiC and GaN will be used for infrastructure such as base stations at frequencies typically above about 2 GHz.

6. Near-term AMS Technology Req’t

7. Long-term AMS Technology Req’t

8. Standards and protocols influence considerably parameters such as operating frequencies, channel bandwidth, and transmit power. • Increased RF performance for silicon is usually achieved by geometrical scaling. Increased RF performance for III-V compound semiconductors is achieved by optimizing carrier transport properties through materials and bandgap engineering. • During the last two decades, technologies based on III-V compounds have established new business opportunities for wireless communications systems. • When high volumes of product are expected, silicon and more recently silicon-germanium replace the III-Vs in those markets for which these group IVs can deliver appropriate performance at low cost.

9. Electronic design and automation (EDA) software tools are not equipped today to handle the integration of the four distinct wireless system building blocks— • analog/mixed-signal (including certain digital functions), • transceiver, • 3) power amplifier, and • 4) power management.

10. RF AND AMS TECHNOLOGIES FORWIRELESS COMMUNICATIONS • ANALOG AND MIXED-SIGNAL • RF TRANSCEIVERS • POWER AMPLIFIERS AND POWER MANAGEMENT • MILLIMETER WAVE

11. ANALOG AND MIXED-SIGNAL 1) analog speed devices 2) analog precision MOS device scaling but with relatively high voltages to achieve high signal to noise ratios and low signal distortion, 3) capacitors, and resistors; all devices are optimized for precision, matching performance, 1/f noise, low non-linearity, and low temperature gradients.

12. RF TRANSCEIVERS 1. Applications are focused on low noise amplifiers (LNAs), frequency synthesis and logic, voltage controlled oscillators (VCO), driver amplifiers, and filters. 2. Devices include NPN (n-type emitter, p-type base, and n-type collector) bipolar transistors, RF-MOS (NMOS) field effect transistors, inductors, varactors, RF capacitors, and resistors. 3. RF transceivers in the 800 MHz to 10 GHz range which covers both local and wide area standards such as global standard for mobile (GSM), code division multiple access (CDMA), wideband CDMA (WCDMA), 802.11 protocol for local area networks, and ultra wideband (UWB).

13. POWER AMPLIFIERS AND POWER MANAGEMENT 1. High voltage devices are used in base station power amplifiers, such as Si LDMOS, GaAs FET, GaAs PHEMT, SiC FET and GaN FET. 2. PAs for terminals that require relatively high breakdown voltage devices [HBTs, PHEMTs, MOSFETs, and bipolars] are included herein. The key driving forces are integration of components and cost.

14. MILLIMETER WAVE • Today, compound semiconductors dominate the 10–100 GHz range. The device types most commonly used for analog MM-wave applications are HEMT, PHEMT, and MHEMT while MESFET and HBT predominate for mixed-signal and high speed applications. • Except for MESFET and SiGe HBT, all device types employ epitaxial layer stacks that are composed of ternary or quaternary compounds derived from column III and V of the periodic chart. • Device properties are critically dependent on the selection of materials, thickness, and doping in the stack, which are proprietary to the manufacturer. • Trade-offs among power, efficiency, breakdown, noise figure, linearity, and other performance parameters abound.

15. 1. Manufacturing non-recurring engineering (NRE) costs are on the order of one million dollars (mask set + probe card); design NRE costs routinely reach tens of millions of dollars, with design shortfalls being responsible for silicon re-spins that multiply manufacturing NRE. 2. Manufacturing cycle times are measured in weeks, with low uncertainty; Design and verification cycle times are measured in months or years, with high uncertainty. 3. Software can account for 80% of embedded-systems development cost; Test cost has grown exponentially relative to manufacturing cost; Verification engineers outnumber design engineers on microprocessor project teams.

16. Challenges due to Silicon complexity ; impact of process scaling, new materials or device/interconnect architectures 1. Non-ideal scaling of device parasitics and supply/threshold voltages (leakage, power management, circuit/device innovation, current delivery) 2. Coupled high-frequency devices and interconnects (noise/interference, signal integrity analysis and management, substrate coupling, delay variation due to cross-coupling) 3. Manufacturing variability (statistical process modeling and characterization, yield, leakage power) 4. Scaling of global interconnect performance relative to device performance (communication, synchronization) 5. Decreased reliability (gate insulator tunneling and breakdown integrity, joule heating and electromigration, single-event upset, general fault-tolerance) 6. Complexity of manufacturing handoff (reticle enhancement and mask writing/inspection flow, NRE cost). 7. Process variability (library characterization, analog and digital circuit performance, error-tolerant design, layout reuse, reliable and predictable implementation platforms)

17. Challenges due to System Complexity ; exponentially increasing transistor counts 1. Reuse (support for hierarchical design, heterogeneous SOC integration especially for analog/mixed-signal) 2. Verification and test (specification capture, design for verifiability, verification reuse for heterogeneous SOC, system-level and software verification, verification of analog/mixed-signal and novel devices, self-test, intelligent noise/delay fault testing, tester timing limits, test reuse) 3. Cost-driven design optimization (manufacturing cost modeling and analysis, quality metrics, co-optimization at diepackage-system levels, optimization with respect to multiple system objectives such as fault tolerance, testability, etc.) 4. Embedded software design (predictable platform-based system design methodologies, codesign with hardware and for networked system environments, software verification/analysis) 5. Reliable implementation platforms (predictable chip implementation onto multiple circuit fabrics, higher-level handoff to implementation) 6. Design process management (design team size and geographic distribution, data management, collaborative design support, “design through system” supply chain management, metrics and continuous process improvement)

18. SoC

19. SoC MARKET DRIVERS I.Portable and Wireless • 1. Size/weight ratio: peak in 2004 • 2. Battery life: peak in 2004 • 3. Function: 2×/2 years • 4. Time-to-market: ASAP II. Broadband • 1. Bandwidth: 2× / 9 months • 2. Function: 20%/yr increase • 3. Deployment/Operation Cost: flat • 4. Reliability: asymptotic 99.999% • 5. Time-in-market: long • 6. Power: W/m3 of system

20. III. Internet Switching • 1. Bandwidth: 4×/3–4 yrs. • 2. Reliability • 3. Time-to-market: ASAP • 4. Power: W/m3 of system IV. Mass Storage • 1. Density: 60% increase/year • 2. Speed: 2× by 2007 • 3. Form factor: shift toward 2.5" V. Consumer • 1. Cost: strong downward pressure • 2. Time-to-market: <12 mos • 3. Function: high novelty • 4. Form factor • 5. Durability/safety • 6. Conservation/ecology

21. VI. Computer 1. Speed: 2×/2 years 2. Memory density: 2×/2 years 3. Power: flat to decreasing, driven by cost and W/m3 4. Form factor: shrinking size 5. Reliability VII. Automotive 1. Functionality 2. Ruggedness (external environment, noise) 3. Reliability and safety 4. Cost

22. First Integration of Technologies in SOC with Standard CMOS Process

23. SOC MULTI-TECHNOLOGY • The need to build heterogeneous systems on a single chip is driven by such considerations as cost, form-factor, connection speed/overhead, and reliability. • Today, a number of technologies (MEMS, GaAs) are more cost-effectively flipped onto or integrated side-by-side with silicon in the same module depending also on the area and pin-count restrictions of the respective product (e.g. Flash, DRAM). • SIP or SoC ?

24. SOC HIGH-PERFORMANCE 1. Examples of SOC-HP include network processors and high-end gaming applications. 2. Historically, chip I/O speed (per-pin bandwidth) has been scaling much more slowly than internal clock frequency due to compatibility with existing slow I/O standards, but the primary limitation has been that unterminated CMOS signals on printed circuit boards are difficult to run at significantly greater than 100MHz due to slow settling times.

25. SOC HIGH-PERFORMANCE 3. During the past decade, high-speed links in technology initially developed for long-haul communication networks have found increasing use in other applications. The high-speed I/O eliminates the slow board settling problems by using point-to-point connections and treating the wire as a transmission line. Today the fastest of these serial links can run at 10Gbit/s per pin. 4. A high-speed link has four main parts: 1) a transmitter to convert bits to an electrical signal that is injected into the board-level wire, 2) the wire itself, 3) a receiver that converts the signal at the end of the wire back to bits, and 4) a timing recovery circuit that compensates for the delay of the wire and samples the signal on the wire at the right place to get the correct data. 5. Broadly speaking, high-speed links are used in optical systems, chip-to-chip connections, and backplane connections.

26. SOC LOW-COST, LOW-POWER • Examples of SOC-LP include portable and wireless applications such as PDAs or digital camera chips. • LOP(Low Operating Power) and LSTP(Low Standby Power)

27. SoC-relatedBusiness Models • Foundry • Independent Device Manufacturer (IDM) • ASSP Provider (Fabless) • IP Provider (Chipless) • System House • Design Service Providers (Design House) • EDA Vendors • Embedded Software Developers • Assembly House (Chipak, ASE, Anam) • Others • Mask House (Dupont,…) • Equipment Manufacturer • Wafer/Materials Supplier

28. Foundry • Silicon foundry offers 0.09+ micron digital + analog, RF, MEMS … • long IP (free, priced) list desirable • MPW runs for prototyping • Reticle generation + fabrication • P&R, testing, packaging service extra • TSMC, UMC, Chartered, SMIC, Dongbu-Anam,..

29. Testing • DFT(Design-for-testability) desirable • Overhead due to test circuitry in speed, area, power  5% • BIST(Built-in Self Test), Full/Partial Scan JTAG for board-level testing • Before/After Packaging/Burn-in

30. 각 나라의 SoC 개발 전략과 현황 • 미국; ITRS, Standard Org., Leading Universities, SIA/Sematech/SRC, Darpa/NSF, MOSIS, VC’s, Nasdaq. • 유럽; Big system industries(Nokia, SGS,Philips,Eriksson,Siemens…), EC consolidation, IMEC • 일본; VDEC/VSAC, Silicon Seabelt, Japan TRS, System Giants (Sony, Toshiba,..) • 이스라엘 ; embedded software, encryption, major research centers. • 대만 ; Si-Soft project • 중국 ; 상해, 심천, 광주, 북경 (BOT system, 국립대) • 인도 ; Bangalore

31. Brilliant Taiwan IC Design & Foundry Source: Dataquest, FSA, ITRI Foundry Ranked 1 Worldwide IC Design Ranked 2 Worldwide, next to USA

32. Unit：USD Million 2001 01/00 00/99 Growth Growth Companies Country % % 2000 2001(e) Rank Nvidia* 1,300 735 76.9% 96.0% U.S 1 9.0% Qualcomm* 1,180 -5.6% 1,250 U.S 2 1,565 U.S Xilinx 1,150 -26.5% 74.0% 3 TW 4 VIA 1,012 984 2.8% 183.0% U.S 5 1,132 962 -15.0% 121.0% Broadcom U.S 6 1,376 839 -39.0% 64.0% Altera U.S 7 Cirrus Logic 534 739 -27.7% 39.0% TW 8 MediaTek 456 411 10.9% 138.0% U.S 9 ATI* 465 711 -34.6% 0.0% U.S 10 SanDisk 366 601 -39.1% 143.0% U.S 11 U.S 12 318 Qlogic 353 11.0% 79.0% U.S 13 PMC-Sierra 323 694 -53.5% 165.0% U.S 14 Lattice 568 295 -48.1% 76.0% U.S 15 SST 294 490 -40.0% 292.0% U.S 16 271 303 -10.6% -3.0% ESS U.S 17 Globespan Virata 270 348 -22.4% 521.0% TW 18 Marvell 252 132 90.9% -- U.S 19 TW 20 216 194 11.3% 74.0% Realtek Legerity* 210 260 -19.2% -- Source: ITIS (2002/03) Note: *Refer to IC Insights statistics Sunplus 197 201 -2.0% 56.0% Worldwide Top 20 Fabless

33. 1999 2000 2001(e) Visibility of Taiwan Fabless 25.9% 20.7% 19.6% % of WW Sales Singapore 6% / H K China 16% Taiwan in WW Top 10 2 1 2 Taiwan in WW Top 20 3 4 4 S Korea 21% Note：SiS became an IDM in 2000, not a fabless thereafter Source：IT IS (2002/03) Taiwan 57% Asia Pacific Fabless Nos. in 2000 Source：Dataquest(2001/10)

34. World Semiconductor Market by Region

35. World Semi Market by Application

36. 한국내 반도체특허 출원 현황

37. 2002(2001) 세계 반도체 매출 top 10 기업

38. 세계 비메모리 매출 Top 10 + 삼성

39. 2001 세계 Micro-components Market Share

40. 2002 ASSP/ASIC M/S World Top 10

41. 2002 Analog 반도체 World Top 10

42. 우리나라 2002-2006 학사 이상 인력 수요

43. 일본의 아스카 프로젝트

44. 일본의 ASPLA Project

45. 각국의 SoC 관련 project

46. Major Issues/Challenges of SoC

47. SoC 가 가져오는 기회 • 고속 성장하는 consumer product 의 특징은 portable, 저전력 소모, 짧은 TTM (Time-to-Market)임. • 이외에도 medical/bio/health, smart home, intelligent building, automotive/vehicle (최신 BMW 에는 processor core 가 1000개 내장됨), military 시장에서도 SoC 의 엄청난 기능/가격비, 성능/전력비는 새 응용을 열고 있다. • 사람의 수명이 길어지고, 출산율은 줄므로 생명과 복지, 교육 시장이 커 진다.

48. SoC 가 가져오는 기회 • 메모리와 마이크로프로세서가 견인해 온 반도체공정과 full custom 설계기술 -> SoC 에 의한 시스템설계와 IP 활용기술이 시장을 주도. • Volume 시장을 target 할 수 밖에 없음. • 0.13 micron 공정의 NRE cost ; $ 1M • 300 mm wafer 공정은 200 mm 의 1.3 배의 비용으로 2.25 배의 chip 을 얻음.

49. SoC 가 주는 도전(Overall) • Market to address; What to design. What are killer applications to justify volume production? • How to deal with many different players. (foundry, EDA vendor, IP vendor, system house, software/firmware/RTOS vendor, test/packaging house,…) • How to reduce the TTM (Time-to-market). • How to reduce the production cost

50. SoC 가 주는 도전(process) • How to integrate various process technologies (MEMS, analog, DRAM). • How to handle/model VDSM (Very Deep Sub-Micron) effect. • Process uniformity, yield, reliability • DFM (Design for Manufacturability)