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DS90LV001

XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky , Matt Warren, Matthew Wing,. A-C Coupling & Latching Test Circuit -1-. -ve LVDS TEST OUTPUT. 4k7. LVDS output. SK26. SK25. 100pF. 8 12 U35 7 11.

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DS90LV001

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  1. XFEL 2D Pixel Clock and Control SystemTrain Builder Meeting, UCL11 May 2010Erdem Motuk,Martin Postranecky, Matt Warren, Matthew Wing,

  2. A-C Coupling & Latching Test Circuit -1- -ve LVDS TEST OUTPUT 4k7 LVDS output SK26 SK25 100pF 8 12 U35 7 11 • 12 • U11 • 7 11 • 7 • U44 • 3 6 100R 100R 100R 2k2 CLK IN 100pF SK16 SK15 4k7 DS90LV110 DS90LV001 DS90LV110 +ve LVDS TEST OUTPUT C+C

  3. 100 MHz clock 100MHz clock 1= IN+ 2= IN- 3= OUT+ latched 4= OUT- latched C+C

  4. Paused Signal LONG PAUSE 3= OUT+ latched 4= OUT-latched C+C

  5. Starting Signal STARTINGSIGNAL 3= OUT+ latched 4= OUT- latched C+C

  6. Pseudo-Random Signal PSEUDO-RANDOM 1= TTL IN 2= OUT+ latched 3= OUT- latched C+C

  7. Pseudo-Random Signal - Start PSEUDO-RANDOM START 1= LVTTL IN 2= OUT+ latched 3= OUT- latched C+C

  8. A-C Coupling & Latching Test Circuit -2- +3v3 1k 1k 4k7 EN 2 8 7 U1 3 6 • EN • 2 8 7 • U2 • 3 6 100pF 5m CAT5 cable 2 1 100R 100R 100R 2k2 100pF 4k7 DS90LV001 DS90LV001 -ve LVDS TEST OUTPUT 3 4 U4 6 3 2 U3 6 7 Pin5 1 +ve LVDS TEST OUTPUT +3v3 100n RJ45 DS90LV001 DS90LV028 C+C

  9. National DS90LV001 • 800 Mbps LVDS Buffer • Diff. Delay = 1.4ns typ. • Part-to-Part Skew = 0ps typ. / 60ps max. ( for same Vcc & temp. ) • Fall / Rise Time = 310ps typ. • Peak-to-Peak Data Jitter = 100ps typ. C+C

  10. Current Tests Differential LVDS Pseudo-random signal from FPGA Development Board ( using 100 MHz clock ) 5 m of CAT5-type cable with RJ45 A-C coupling & latching test circuit -2- Differential LVDS Test Output fed back to FPGA Development Board Compare and log errors C+C

  11. Future Plans • Finish testing AC-coupling & Latching test circuit -2- • Yes / No decision on balanced signals ( Manchester coding ) ~2 weeks • Final FPGA selection ( PLL, Delays ) • Finalise Circuit Design of C&C prototype board ~ July 2010 • Prototype board selection ( DESY ? / RAL ? ) • Schematic entry & layout ( RAL ) ~ August - September 2010 • C&C Prototype Mk.1 manufacture ~ October 2010 C+C

  12. Single Integrated Prototype Card Fanout 8 To FEE FPGA TR / Machine etc. Signals or inputs from C&C Master Outputs to Fanouts Master TCP/ IP Local AMC Control PLL etc C+C

  13. End….. C+C

  14. Overview Bunch Veto μTCA Crate FEE 99.3058 MHz Clock C+C Master C+C Fanout Slave FEE 4 FEE C+C Fanout FEE Start/Info/Stop Crate Processor C+C Fanout C+C Fanout Bunch Veto FEE Status 4 Trigger + Telegram ID 1-20MHz? Clock 4.5139 MHz Clk Trig/Data MINIMUM FANOUT REQUIREMENTS : 16 + Fanouts, expandable 3x Outputs ( diff. LVDS, STP/UTP ) 1x Input ( single line, level only ) Timing Receiver Timing Interface XFEL Other C+C

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