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ADSP21xx

ADSP21xx. By: Parmeshwar Kumar 90210411373 Btech ECE 6 th semester. Features . 16-bit fixed point DSP microprocessors Enhanced Harvard architecture for three bus performance Integrated timer Low profile IDLE instruction Separate on chip bus for program and data

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ADSP21xx

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  1. ADSP21xx By: Parmeshwar Kumar 90210411373 Btech ECE 6th semester Param Kumar

  2. Features • 16-bit fixed point DSP microprocessors • Enhanced Harvard architecture for three bus performance • Integrated timer • Low profile IDLE instruction • Separate on chip bus for program and data • Dual data address generators • Three computational units: ALU,MAC, shifter • Automatic booting on chip memory • Single cycle instruction excection • 25MIPS, 40ns maximum instruction rate Param Kumar

  3. Param Kumar

  4. Internal Architecture The architecture contains the following main units…. • Arithmetic Logic Unit(ALU) • Multiplier accumulator(MAC) • Barrel Shifter • Register file • Data address generators • Program sequence • Cache Memory • Bus Exchange Param Kumar

  5. ALU • Sample ALU instructions • A+B, • Absolute value -|A| • Average: [A+B]/2 • Logical AND , OR, or NOT etc It generates six status flags > AZ, AV, AN, AC, AS, AI, AF, CACC Param Kumar

  6. MAC(Multiplier Accumulator) Features… • 32/40-bit floating-point multiplier • Multiplier used with ALU • It is used for 1 cycle pipelined MAC • 32/40 bit floating point multiplication • 40 bit results. • 32-bit Fixed point MAC • 64-bit results ,integer and fractional • 80-bit dual accumulators • 32 bit results store to a register file Param Kumar

  7. Barrel Shifter • Arithmetic and logical shifts • Word rotates • Field manipulations • Bit set/clear/toggle/test. Param Kumar

  8. Register file • For transferring data between computation Units and memory and for storing intermediate results. • It transfer 9 words per cycle. Param Kumar

  9. Data Address Generators • It provides optional bit reversal capability. • Automatic address modification • Provide indirect addressing capability • Modulo address modification for addressing circular buffers • Independent and simultaneous address for both program and data. • It have three registers files… • Modify(M) register file • Index(I) register file • Length(L) register file Param Kumar

  10. Program Sequencer • It generates addresses for the instructions. • It provides flexible control of the program flow. • It has six status registers as follows… • Arithmetic status register(ASTAT) • Stack Status register(SSTAT) • Mode status register(MSTAT) • Interrupt control register (ICNTL) • Interrupt mask register(IMASK) • Interrupt force and clear register(IFC) Param Kumar

  11. Cache Memory In computer science it is a short-term memory in a computer with quick access A cache is intended to speed up access to a set of data. It is piece of memory that is faster , more expensive, and smaller. It is used to store previous 16 executed instructions. It keeps track of program memory addresses of instruction stored in the cache memory. Param Kumar

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