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达芬奇及 EVM 板原理图介绍

达芬奇及 EVM 板原理图介绍. 达芬奇＝ DSP64X+ 内核 ＋ ARM 9 内核 1.DSP 核内部结构 32 K L1 Program RAM/CACHE 80K L1 Data RAM/CACHE 64K L2 Unified Mapped RAM/CACHE 2.ARM9 内核 32 BIT ARM 指令 、16 BIT Thumb 指令 16 K 指令 CACHE，8K 数据 CACHE 16K RAM，8K ROM DSP 和 ARM 均小端模式 3. 视频处理子系统 ：视频前端和视频后端.

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达芬奇及 EVM 板原理图介绍

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  1. 达芬奇及EVM 板原理图介绍 达芬奇＝DSP64X+ 内核 ＋ARM 9 内核 1.DSP核内部结构 32K L1 Program RAM/CACHE 80K L1 Data RAM/CACHE 64K L2 Unified Mapped RAM/CACHE 2.ARM9 内核 32 BIT ARM 指令 、16 BIT Thumb 指令 16K 指令CACHE，8K 数据 CACHE 16K RAM，8K ROM DSP 和 ARM 均小端模式 3. 视频处理子系统 ：视频前端和视频后端

  2. 先介绍下DSP 子系统

  3. DSP子系统 DSP 内核为标准的TI的TMS320C64x+ 模块和L1P, L1D, and L2 Features of the C6000： 1.Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units 2. Instruction packing 3. Conditional execution of most instructions 4. Efficient code execution on independent functional units 5. 8/16/32-bit data support, providing efficient memory support for a variety of applications 6.40-bit arithmetic options add extra precision for vocoders and other computationally intensive applications 7. Saturation and normalization provide support for key arithmetic operations 8. Field manipulation and instruction extract, set, clear, and bit counting support a common operation found in control and data manipulation applications

  4. additional features of the C6000： 1. Each multiplier can perform two 16 ´ 16-bit or four 8 ´ 8-bit multiplies every clock cycle 2. Quad 8-bit and dual 16-bit instruction set extensions with data flow support 3. Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses 4.Special communication-specific instructions to address common operations in error-correcting codes 5. Bit count and rotate hardware extends support for bit-level algorithms 6. Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code size 7. Protected mode operation: a two-level system of privileged program execution to support higher capability operating systems and system features, such as memory protection 8. Exceptions support for error detection and program redirection to provide robust code execution 9. Hardware support for modulo loop operation to reduce code size

  5. DSP 框图如下

  6. DSP MemoryControllers · Program memory controller (PMC) · Data memory controller (DMC) · Unified memory controller (UMC) • External memory controller (EMC) • internal DMA (IDMA) controller Internal Peripherals · Interrupt controller (INTC) • Power-down controller (PDC) External Memory

  7. Dsp 中断向量表

  8. ARM–DSP Integration · Shared peripherals: – ARM and DSP have access to EDMA – ARM and DSP have access to ASP – ARM and DSP have access to Timer 0 and Timer 1 · Shared memory: – ARM can access DSP internal memory – DSP can access ARM internal memory – ARM and DSP can access DDR2 port and asynchronous EMIF · ARM–DSP interrupts: – ARM can interrupt the DSP (via four general interrupts and one NMI) – DSP can interrupt the ARM (via two general interrupts) · As system master, the ARM may manage the following DSP functions: – Boot the DSP – DSP power management – Enable/disable the DSP clock – Reset the DSP DSP Boot

  9. 以上是对达芬奇DSP 子系统的简介。 下面介绍下ARM 子系统！

  10. ARM子系统 ARM子系统扮演着全局系统的控制角色。例如产生系统任务，系统初始化，各种配置信息，电源管理，用户接口和用户代码指令的执行，DSP子系统的工作，以及VPSS 视频处理子系统的控制等。 Components of the ARM Subsystem · ARM926EJ-S RISC processor, including: – Co-Processor 15 (CP15) – MMU – 16KB Instruction cache and 8KB Data cache – Write Buffer · ARM Internal Memories – 16KB Internal RAM (32-bit wide access) – 8KB Internal ROM (ARM bootloader for non-AEMIF boot options) · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) · System Control Peripherals – ARM Interrupt Controller – PLL Controller – Power and Sleep Controller – System Module

  11. The ARM also manages/controls the following peripherals: · DDR2 Port Controller · Asynchronous EMIF (AEMIF) Controller, including the NAND flash interface · Enhanced DMA (EDMA) System - Channel Controller (CC) and Transfer Controllers (TCs) · UARTs · Timers · Pulse Width Modulator (PWM) · Inter-IC Communication (I2C) · Multimedia Card/Secure Digital (MMC/SD) Card Controller · Audio Serial Port (ASP) · Universal Serial Bus (USB) Controller · ATA/Compact Flash (CF) Controller • Serial Port Interface (SPI) · Ethernet Media Access Controller (EMAC) · Video Processing Front End (VPFE): – CCD Controller (CCDC) – Preview Engine – Resizer – H3A Engine (Hardware engine for – Histogram · Video Processing Back End (VPBE): – On-Screen Display (OSD) – Video Encoder Engine (VENC)

  12. ARM Subsystem Block Diagram

  13. The ARM core consists of the following components: · ARM926EJ-S - 32-bit RISC processor · 16-KB Instruction cache · 8-KB Data cache · MMU · CP15 to control MMU, cache, etc. · Java accelerator · ARM Internal Memory – 16-KB built-in RAM – 8-KB built-in ROM (boot ROM) · Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) · Features: – The main write buffer has a 16-word data buffer and a 4-address buffer – Support for 32/16-bit instruction sets – Fixed little endian memory format – Enhanced DSP instructions

  14. The ARM can operate in the following modes: · User mode (USR): Non-privileged mode, usually for the execution of most application programs. · Fast interrupt mode (FIQ): Fast interrupt processing · Interrupt mode (IRQ): Normal interrupt processing · Supervisor mode (SVC): Protected mode of execution for operating systems · Abort mode (ABT): Mode of execution after a data abort or a pre-fetch abort · System mode (SYS): Privileged mode of execution for operating systems · Undefined mode (UND): Executing an undefined instruction causes the ARM to enter undefined mode. Exceptions and Exception Vectors · Reset exception: processor reset · FIQ interrupt: fast interrupt · IRQ interrupt: normal interrupt · Abort exception: abort indicates that the current memory access could not be completed. The abort could be a pre-fetch abort or a data abort. · SWI interrupt: use software interrupt to enter supervisor mode. · Undefined exception: occurs when the processor executes an undefined instruction

  15. ARM异常向量表 ARM 指令： · ARM mode or 32-BIS: the standard 32-bit instruction set · Thumb mode or 16-BIS: a 16-bit instruction set

  16. 时钟域框图介绍

  17. The DM644x ARM Interrupt Controller (AINTC) has the following features: · Supports up to 64 interrupt channels (16 external channels) · Interrupt mask for each channel · Each interrupt channel is mappable to a Fast Interrupt Request (FIQ) or to an Interrupt Request (IRQ) type of interrupt. · Hardware prioritization of simultaneous interrupts · Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ) · Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time

  18. 以上介绍的是ARM 子系统 下面介绍下VPSS 视频子系统

  19. 嵌入视频子系统VPSS 1.VPFE 视频前端 提供视频输入接口，例如图象传感器，视 频解码器等 2.VPBE 视频后端 提供视频输出接口，例如LCD ,SDTV， HDTV 等

  20. VPSS 框图

  21. VPFE 组成部分 – The CCD controller provides an interface to image sensors and digital video sources. – The preview engine ISP is a parameterized hard-wired image processing block whose image processing functions can be customized for each sensor type to realize good image quality and video frame rates for displays and video recording modes. – The resizer module provides a means to size the input image data to the desired display or video encoding resolution. – The H3A module is designed to support the control loops for auto focus (AF), auto white balance(AWB), and auto exposure (AE) by collecting metrics on the raw image data from the CCD controller. – The histogram module bins input color pixels, depending on the amplitude, and provides statistics required to implement various H3A (AE/AF/AWB) algorithms and tune the final image/video output The histogram module can operate on raw image data from CCD controller or DDR2.

  22. CCD Controller (CCDC) · Conventional Bayer pattern sensor formats. · Generates HD/VD timing signals and field ID to an external timing generator or synchronizes to the external timing generator. · Support for progressive and interlaced sensors (hardware support for up to 2 fields). · Support for up to 75 MHZ sensor clocks · Support for REC656/CCIR-656 standard (YCbCr 422 format, either 8-bit or 16-bit). · Support for YCbCr 422 format, either 8- or 16-bit with discrete H and VSYNC signals. · Support for up to 16-bit input. · Generates optical black clamping signals. · Support for digital clamping and black level compensation. · Support for 10-bit to 8-bit A-law compression. · Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left and right edges of each line are cropped from the output. · Support for generating output to range from 16-bits to 8-bits wide (8-bits wide allows for 50% saving in storage area). · Ability to control output to the DDR2 via an external write enable signal. · Support for up to 16K pixels (image size) in both the horizontal and vertical directions.

  23. Preview Engine – Hardware Image Signal Processor (ISP) · Conventional Bayer pattern. · Accepting the input image/video data from either the CCD/CMOS controller or the SDRAM/DDRAM. · An output width of up to 1280 pixels wide. · Simple horizontal averaging (by factors of 2, 4, or 8) to handle input widths that are greater than 1280 (plus the cropped number) pixels wide. · Ability to capture a dark frame (instead of applying the conventional image processing to the raw data) and store it in the SDRAM/DDRAM. · Ability to subtract a dark frame (fetched from the SDRAM/DDRAM memory) for every input raw data frame pixel-by-pixel to improve video quality. · Ability to perform lens shading compensation instead of the dark frame subtract. Each input pixel is multiplied with a corresponding 8-bit gain value and the result is right shifted by a programmable parameter (0-7 bits). · Support for A-law decompression to transform non-linear 8-bit data to 10-bit linear data. This feature, which allows data in the SDRAM/DDRAM to be 8-bits only, saves 50% of the area if the input to the preview engine is from the SDRAM/DDRAM. · A horizontal median filter for reducing temperature induced noise in pixels. · A programmable noise filter that operates on a 3 ´ 3 grid of the same color (effectively, this is a five line storage requirement). · Digital gain and white balance (color separate gain for white balance). · Programmable RGB-to-RGB blending matrix (9 coefficients for the 3 ´ 3 matrix). · Fully programmable gamma correction (1024 entries for each color held in an on-chip RAM). · Programmable color conversion (RGB to YUV) coefficients (9 coefficients for the 3 ´ 3 matrix). · Luminance enhancement (non-linear) and chrominance suppression and offset.

  24. Resizer · Maximal output width of 1280 horizontal pixels · Support for up to 4´ upsampling (digital zoom). · Support for up to 1/4´ downsampling (reducing image size to store more pictures in the memory card) · There are further constraints for real-time preview-output resizing due to the limited on-chip memory and processing resources. Horizontal resizer stage output rate is limited to resizer_clock/2. · Support for resizing either YUV 422 packed data (16-bits) or color separate data (assumed to be 8-bit data) that is contiguous. The input source for the color separate data should be the DDR2. · Separate/independent resizing factor for the horizontal and vertical directions. · Available upsampling and downsampling ratios are: 256/N, with N ranging from 64 to 1024. · Programmable luminance sharpening after the horizontal resizing and before the vertical resizing step.

  25. Hardware 3A (H3A) two main blocks in the H3A module: · Auto focus (AF) engine • Auto exposure (AE) and auto white balance (AWB) engine Auto Focus (AF) Engine · Support for a Peak Mode in a paxel (a paxel is defined as a two-dimensional block of pixels). · Accumulate the maximum Focus Value of each line in a paxel · Support for an accumulation/sum mode (instead of peak mode). · Accumulate focus value in a paxel. · Support for up to 36 paxels in the horizontal direction and up to 128 paxels in the vertical direction. The number of horizontal paxels is limited by the memory size, while the vertical number of paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of paxels in vertical direction. · Programmable width and height for the paxel. All paxels in the frame are the same size. · Programmable red, green, and blue position within a 2 ´ 2 matrix. · Separate horizontal start for paxel and filtering. · Programmable vertical line increments within a paxel. · Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11 coefficients each). The filters compute the sharpness/peaks in the frame to focus on.

  26. Auto Exposure (AE) and Auto White Balance (AWB) Engine · Accumulate clipped pixels along with all non-saturated pixels · Support for up to 36 horizontal windows. · Support for up to 128 vertical windows. · Programmable width and height for the windows. All windows in the frame are the same size. · Separate vertical start coordinate and height for a black row of paxels that is different than the remaining color paxels. · Programmable horizontal sampling points in a window · Programmable vertical sampling points in a window

  27. Histogram · Support for up to four regions/areas. – Each region has its own horizontal/vertical start and end position – When regions overlap, pixels from the overlapped area are accumulated into the highest priority region only (the priority is region0 > region1 > region2 > region3) · Support for conventional Bayer pattern sensors. Each region is capable of accumulating 4 colors separately. · Support for 32, 64, 128, or 256 bins per color per region. · Support for automatic clear of the histogram RAM once the ARM reads that location (programmable register). · Support for saturation of the pixel count if the count exceeds the maximum value that the memory location can hold (each memory location is 20-bits wide). · Support for a downshift ranging from 0 to 7 bits (this implies that the maximum range of each bin will be 128). · The last bin (highest range of values) will accumulate any value that is higher than the lower bound. For example, if 32 bins are set up so that each bin accumulates a range of 8 or a downshift of 3 (0 to 7, 8 to 15, etc.), the last bin shall accumulate all values higher than 248 and not just the range of values from 248 to 255.

  28. 视频后端VPBE · On-screen display (OSD) graphic accelerator: The OSD manages display data in various formats for several types of hardware display windows and it also handles blending of the display windows into a single display frame, which the video encoder (VENC) module then outputs. · Video encoder (VENC): The VENC takes the display frame from the on-screen display (OSD) and formats it into the desired output format and output signals (including data, clocks, sync, etc.) that are required to interface to display devices. The VENC consists of three primary sub-blocks: – The analog video encoder generates the signaling to interface to NTSC/PAL television displays, including video A/D conversion. – The digital LCD controller supports interfaces to various digital LCD display formats as well as standard digital YUV outputs to interface to high-definition video encoders and/or DVI/HDMI interface devices. – Timing generator to generate the specific timing required for analog video output as well as various digital video output modes.

  29. On-Screen Display (OSD) Features · Support for two video windows and two OSD windows that can be displayed simultaneously (VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1). · Separate enable/disable control for each window. · Programmable width, height, and base starting coordinates for each window. · External memory address and offset registers for each window. · Support for ´2 and ´4 zoom in both the horizontal and vertical direction. · Can configure OSDWIN1 to be an attribute window for OSDWIN0. · Ability to select either field/frame mode for the windows (interlaced/progressive). · An eight-step blending process between the OSD and video windows. · Transparency support for the OSD and video data (blending between bitmap and video only for pixels matching the background color). · Ability to resize from VGA to NTSC/PAL (640 ´ 480 to 720 ´ 576) for both the OSD and video windows. · Reads in YCbCr data in 422 format from the external memory with the ability to interchange the order of the CbCr component in the 32-bit word (this is relevant to the two video windows). · Support for a ping-pong buffer scheme that you can use for VIDWIN0 (this allows you to access video data from two different locations in the SDRAM/DDRAM).

  30. On-Screen Display (OSD) Features The OSD window (either one, but not both at the same time) is capable of reading in RGB data (16-bit data with six bits for the green and five bits each for the red and blue colors) instead of bitmap data in YCbCr format restricted to a maximum of 8-bits. · The OSD bitmap data width is selectable between 1 bit, 2 bits, 4 bits, or 8 bits. · Each OSD window supports 16 entries for the bitmap (to index into a 256 entry RAM/ROM CLUT table). · Indirect support for 24-bit RGB input data (which will be transformed into 16-bit YCbCr video window data) via the wrapper interface in the VPBE. · A programmable background color selection. · Programmable color palette with the ability to select between a RAM/ROM table with support for 256 colors. There are 2 ROM tables from which one can be selected for all the windows together. · The width, height, and color of the cursor is selectable.

  31. The following restrictions exist in the OSD module: · Both the OSD windows and VIDWIN1 should be fully contained inside VIDWIN0. · The OSD cannot support more than 256 color entries in the CLUT RAM/ROM. Some applications require higher number of entries, and one workaround is to use VIDWIN1 as an overlay mimicking the OSD window. Another option is to use the RGB mode for one of the OSD windows, which allows for a total of 16-bits for the R, G, and B colors (64K colors). · The OSD can only read YCbCr in 422 interleaved format for the video windows. Other formats, either color separate storage or 444/420 interleaved data is not supported. · If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window dimension cannot be greater than 720 currently. This is due to the limitation in the size of the line memory. · It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM while another chooses ROM. · The 24-bit RGB input mode is only valid for one of the two video windows (programmable) and does not apply to the OSD windows.

  32. Video Encoder (VENC) Features · Master Clock Input - 27 MHZ (´2 Upsampling) · SDTV Support – Composite NTSC-M, PAL-B/D/G/H/I – S-Video (Y/C) – Component YPbPr (SMPTE/EBU N10, Betacam, MII) – RGB – Macrovision (Rev7.1) Anticopy Protection – Non-Interlace – CGMS/WSS – Line 21 Closed Caption Data Encoding – Chroma Low-Pass Filter 1.5 MHZ/3 MHZ – Programmable SC-H phase · HDTV Support – Progressive Output (525p/625p) – Component YPbPr – RGB – CGMS/WSS – Macrovision (Rev1.2) Anticopy Protection for 525p/625p YPbPr

  33. Video Encoder (VENC) Features · 10-bit Over-Sampling D/A Converters (54MHz) · Optional 7.5% Pedestal · 16-235/0-255 Input Amplitude Selectable · Programmable Luma Delay · Master/Slave Operation · Internal Color Bar Generation (100%/75%) The digital LCD interface features are: · Programmable DCLK · Various Output Formats – YCbCr 16 bit – YCbCr 8 bit – ITU-R BT. 656 – Parallel RGB 24 bit · Low-Pass Filter for Digital RGB Output · Programmable Timing Generator · Master/Slave Operation · Internal Color Bar Generation (100%/75%)

  34. VPBE 框图

  35. 达芬奇处理器资源介绍 异步外部存储器接口：16BIT 宽度，可扩展SRAM， NOR FLASH ，NAND FLASH ASP 音频串口： 可以接音频编解码芯片，扩展音频输入和输出 ATAPI /CF主机标准接口：可扩展硬盘，CF卡，光驱等 DDR2 存储器控制器：可扩展高速DDR2 存储器 EDMA 外部DMA 控制器 EMAC 控制器：支持10/100M EMAC接口 GPI0： 多达71个I/O I2C 控制器：一个主机/丛机 IDMA 内部DMA访问控制器 INTC中断控制器 SD/MMC CARD控制器 PDC控制器：省电模式控制器 PWM 脉宽调制控制器 SPI接口控制器：支持两个SPI 设备 TIMER 控制器 UART 控制器 WTD 看门狗控制器 USB2.0 主机、设备接口 VLYNQ

  36. 下面详细查看外设介绍，加强对外设的认识！

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