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Microcontroller and Embedded Systems. Lecture 2. Brief History of 8051. The first microprocessor 4004 was invented by Intel Corporation. 8085 and 8086 microprocessors were also invented by Intel. In 1981, Intel introduced an 8-bit microcontroller called the 8051 .
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Microcontroller and Embedded Systems Lecture 2
Brief History of 8051 • The first microprocessor 4004 was invented by Intel Corporation. • 8085 and 8086 microprocessors were also invented by Intel. • In 1981, Intel introduced an 8-bit microcontroller called the 8051. • It was referred as system on a chip because it had • 128 bytes of RAM, • 4K byte of on-chip ROM, • two timers, • one serial port, and • 4 ports (8-bit wide), all on a single chip. • When it became widely popular, Intel allowed other manufacturers to make and market different flavors of 8051 with its code compatible with 8051. • It means that if you write your program for one flavor of 8051, it will run on other flavors too, regardless of the manufacturer. • This has led to several versions with different speeds and amounts of on-chip RAM.
Features of 8051 Microcontroller • An 8051 microcontroller comes bundled with the following features − • 64K bytes on-chip program memory (ROM) • 128 bytes on-chip data memory (RAM) • Four register banks • 128 user defined software flags • 8-bit bidirectional data bus • 16-bit unidirectional address bus • 32 general purpose registers each of 8-bit • 16 bit Timers (usually 2, but may have more or less) • Three internal and two external Interrupts • Four 8-bit ports,(short model have two 8-bit ports) • 16-bit program counter and data pointer • 8051 may also have a number of special features such as UARTs, ADC, Op-amp, etc. • Full duplex serial data transmitter/ receiver • On chip Oscillator and clock circuits
In 8051, I/O operations are done using four ports and 40 pins. • The following pin diagram shows the details of the 40 pins. • I/O operation port reserves 32 pins where each port has 8 pins. • The other 8 pins are designated as Vcc, GND, XTAL1, XTAL2, RST, EA (bar), ALE/PROG (bar), and PSEN (bar).
I/O Ports and their Functions • The four ports P0, P1, P2, and P3, each use 8 pins, making them 8-bit ports. • Upon RESET, all the ports are configured as inputs, ready to be used as input ports. • When the first 0 is written to a port, it becomes an output. • To reconfigure it as an input, a 1 must be sent to a port.
Port 0 (Pin No 32 – Pin No 39) • It has 8 pins (32 to 39). • It can be used for input or output. • Unlike P1, P2, and P3 ports, we normally connect P0 to 10K-ohm pull-up resistors to use it as an input or output port being an open drain. • It is also designated as AD0-AD7, allowing it to be used as both address and data. • ALE (Pin no 31) indicates if P0 has address or data. • When ALE = 0, it provides data D0-D7, but when ALE = 1, it has address A0-A7. • In case no external memory connection is available, P0 must be connected externally to a 10K-ohm pull-up resistor.
Port 1 (Pin 1 through 8) • It is an 8-bit port (pin 1 through 8) and can be used either as input or output. • It doesn't require pull-up resistors because they are already connected internally. • Upon reset, Port 1 is configured as an input port. • The following code can be used to send alternating values of 55H and AAH to Port 1.
Port 1 (Pin 1 through 8) If Port 1 is configured to be used as an output port, then to use it as an input port again, program it by writing 1 to all of its bits as in the following code.
Port 2 (Pin 21 through 28) • Port 2 occupies a total of 8 pins (pins 21 through 28) and • can be used for both input and output operations. • Just as P1 (Port 1), P2 also doesn't require external Pull-up resistors because they are already connected internally. • It must be used along with P0 to provide the 16-bit address for the external memory. • So it is also designated as (A0–A7), as shown in the pin diagram. • When the 8051 is connected to an external memory, it provides path for upper 8-bits of 16-bits address, and it cannot be used as I/O. • Upon reset, Port 2 is configured as an input port. • The following code can be used to send alternating values of 55H and AAH to port 2.
Port 2 (Pin 21 through 28) If Port 2 is configured to be used as an output port, then to use it as an input port again, program it by writing 1 to all of its bits as in the following code.
Port 3 (Pin 10 through 17) • It is also of 8 bits and can be used as Input/Output. • This port provides some extremely important signals. • P3.0 and P3.1 are RxD (Receiver) and TxD (Transmitter) respectively and are collectively used for Serial Communication. • P3.2 and P3.3 pins are used for external interrupts. • P3.4 and P3.5 are used for timers T0 and T1 respectively. • P3.6 and P3.7 are Write (WR) and Read (RD) pins. • These are active low pins, means they will be active when 0 is given to them and these are used to provide Read and Write operations to External ROM in 8031 based systems.
Dual Role of Port 0 and Port 2 Dual role of Port 0 − Port 0 is also designated as AD0–AD7, as it can be used for both data and address handling. While connecting an 8051 to external memory, Port 0 can provide both address and data. The 8051 microcontroller then multiplexes the input as address or data in order to save pins. Dual role of Port 2 − Besides working as I/O, Port P2 is also used to provide 16-bit address bus for external memory along with Port 0. Port P2 is also designated as (A8– A15), while Port 0 provides the lower 8-bits via A0–A7. In other words, we can say that when an 8051 is connected to an external memory (ROM) which can be maximum up to 64KB and this is possible by 16 bit address bus because we know 216 = 64KB. Port2 is used for the upper 8-bit of the 16 bits address, and it cannot be used for I/O and this is the way any Program code of external ROM is addressed.
Architectural block diagram
It consists of a Central Processing Unit • Two kinds of memory (data RAM plus program ROM/EPROM) Input/Output ports • The mode status, and data registers and random logic needed for a variety of peripheral functions. • These elements communicate through an eight bit data bus which runs throughout the chip referred as internal data bus. This bus is buffered to the outside world through an I/O port when memory or I/O expansion is desired.
Central Processing Unit (CPU): • eight-bit Arithmetic and Logic unit with associated registers like A, B, PSW, SP • the sixteen bit program counter and “Data pointer” (DPTR) registers. • ALU: • perform arithmetic and logic functions on eight bit variables. • The arithmetic unit can perform addition, subtraction, multiplication and division. • The logic unit can perform logical operations such as AND, OR, and Exclusive-OR, as well as rotate, clear, and complement. • The ALU also looks after the branching ‘decisions. An important and unique feature of the Intel 8051 Architecture and 8031 Architecture is that the ALU can also manipulate one bit as well as eight-bit data types. Individual bits may be set, cleared, complemented, moved, tested, and used in logic computation.
Accumulator: • It is an 8-bit register. • It holds a source operand and receives the result of the arithmetic instructions (addition, subtraction, multiplication, and division). • The accumulator can be the source or destination for logical operations and a number of special data movement instructions, including look-up tables and external RAM expansion. • Several functions apply exclusively to the accumulator : rotate, parity computation, testing for zero, and so on. • In addition to accumulator, an 8-bit B-register is available as a general purpose register when it is not being used for the hardware multiply/divide operation.
Program Status Word: • Many instructions implicitly or explicitly affect (or are affected by) several status flags, which are grouped together to form the Program Status Word. • It is an 8-bit word, containing the information as follows.
Other CPU Registers: • Stack Pointer : • The stack pointer register is 8 bit wide. • It is incremented before data is stored during PUSH and ALL instructions. • The stack array can reside anywhere in on-chip RAM. • The stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H. • Data Pointer (DPTR) : • The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). • Its function is to hold a 16 bit address. • It may be manipulated as a 16 bit data register or as two independent 8 bit registers. • It serves as a base register in indirect jumps, lookup table instructions and external data transfer.
Memory Organization: • It can access upto 64 K program memory and 64 K data memory. • The 8051 has 4 Kbytes of internal program memory and 256 bytes of internal data memory. • Each memory type has different addressing mechanism, different control signals, and a different function. • Each may be added independently, and each uses the same address and data buses, but with different control signals.
Program Memory : • when the EA pin is connected to Vcc, program fetches to addresses 0000H through OFFFH are directed to the internal ROM and program fetches to addresses 1000H through FFFFH are directed to external ROM/EPROM. • On the other hand when EA pin is grounded, all addresses (0000H to FFFFH) fetched by program are directed to the external ROM/EPROM.
Accessing External Program Memory • The PSEN signal is used to activate output enable signal of the external ROM/EPROM • The port 0 is used as a multiplexed address/data bus. • It gives lower order 8-bit address in the initial T-cycle and later it is used as a data bus. • The 8-bit address is latched using external latch and ALE signal generated by Intel 8051 Architecture. • The port 2 provides the higher order 8-bit address.
Interrupt /Vector locations in the lower part of program memory • The lower part of program memory stores the vector addresses for various interrupt service routines. • Each interrupt is assigned with a fixed location in program memory. • If interrupt is going to be used, its service routine must begin at corresponding location. If the interrupt is not going to be used, its service location is available as general purpose program memory. • For example, • external interrupt 0 is assigned to location 0003H. • The interrupt service locations are spaced at 8-byte intervals such as 0003H for External Interrupt 0, • 000BH for Timer 0, • 0013H for External Interrupt 1, • 001BH for Timer1,
Interrupt /Vector locations in the lower part of program memory
Data Memory • The 8051 can address upto 64 Kbytes of external data memory. • The “MOVX” instruction is used to access the external data memory. • The internal data memory space for Intel 8051 Architecture and 8031 Architecture is divided into three blocks : • Lower 128 bytes, Upper 128 bytes and SFRs. • The upper addresses and SFRs occupy the same block of address space, 80H through FFH, although they are physically separate entities. • The upper address space is accessible by indirect addressing only and SFRs are accessible by direct addressing only. • Lower address space can be accessed either by direct addressing or by indirect addressing.
Accessing External Data Memory • The multiplexed address/data bus provided by port 0 is demultiplexed by external latch and ALE signal. • Port 2 gives the higher order address bus. The RD and WR signals from 8051 selects the memory read and memory write operation, respectively.
In addition to the program and data memory, • there is another physical address space, some of these – • B, • SP, • PSW, • DPH and DPL registers are discussed earlier. • Others-I/O ports and peripheral function registers collectively referred as special function registers will be introduced in the next sections.
Special Function Register • 8051 uses memory mapped I/O through a set of special function registers that are implemented in the address space immediately above the 128 bytes of RAM. • All access to • the four I/O ports, • the CPU registers, • interrupt-control registers, • the timer/counter, UART, and • power control are performed through registers between 80H and FFH.
SFR Bit Address RAM bit Address
Input Output Port • The MCS-51 family I/O port structure is extremely versatile. • The 8051 has 32 I/0 pins configured as four eight-bit parallel ports ( P0, P1, P2, and P3 ). • All four ports are bidirectional, i.e. each pin will be configured as input or output (or both) under software control. • Each port consists of a latch, an output driver, and an input buffer. • The output drives of Ports 0 and 2 and the input buffers of Port 0, are used in access to external memory. • Port 0 outputs the low order byte of the external memory address, time multiplexed with the data being written or read, Port 2 outputs the high order byte of the external memory address when the address is 16 bits wide. • Otherwise Port 2 gives the contents of special function register P2. • All port pins of Port 3 are multi functional. • They have special functions including two external interrupts, two counter inputs, two special data lines and two timing control strobes.
