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HW/SW Co-design

HW/SW Co-design. Lecture 3: Lab 1 – Getting Started with the Tools. Course material designed by Professor Yarsun Hsu, EE Dept, NTHU RA: Yi-Chiun Fang, EE Dept, NTHU. Outline. Hardware Configuration Software Configuration. HARDWARE CONFIGURATION. Build FPGA Bitstream (1/3).

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HW/SW Co-design

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  1. HW/SW Co-design Lecture 3: Lab 1 – Getting Started with the Tools Course material designed by Professor Yarsun Hsu, EE Dept, NTHU RA: Yi-Chiun Fang, EE Dept, NTHU

  2. Outline • Hardware Configuration • Software Configuration

  3. HARDWARE CONFIGURATION

  4. Build FPGA Bitstream (1/3) • Obtain the GRLIB package here • Used version: grlib-gpl-1.0.19-b3188.tar.gz • Put the file under your home directory • Start Cygwin • tar zxf grlib-gpl-1.0.19-b3188.tar.gz • cd grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/ • make distclean

  5. Build FPGA Bitstream (2/3) • make xconfig (under grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/) • A GUI-based Design Configuration tool will pop up • We can use this tool to set up the basic configuration of our co-designed system • VHDLDebugging → Turn on “Accelerated UART Tracing” • Processor → Debug Support Unit → Turn off “Instruction trace buffer” & “AHB trace buffer” • Debug Link → MSB 16 bits of IP address = 0A00 • Debug Link → LSB 16 bits of IP address = 000A • Save and Exit

  6. Build FPGA Bitstream (3/3) • make ise | tee ise_log (under grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/) • Cygwin will call ISE for HDL synthesis and generate the corresponding bitstream file • You can view the file “ise_log” for the output information of the whole process for further details • The process may lastfrom 40min to longerthan an hourdepending on yourmachine and thehardware design

  7. Configure FPGA (1/5) • Turn on the GR-XC3S-1500 Dev. Board • Open Xilinx iMPACT • Choose “create a new project (.ipf)”

  8. Configure FPGA (2/5) • Choose “Configure devices using Boundary-Scan (JTAG)”

  9. Configure FPGA (3/5) • Choose “Bypass” for devices xcf04s & xcf01s • Choose grlib-gpl-1.0.19-b3188/designs/leon3-gr-xc3s-1500/leon3mp.bit in your Cygwin home directory for device xc3s1500

  10. Configure FPGA (4/5) • Right click on the xc3s1500 icon, and then choose “Program” • Press “OK”

  11. Configure FPGA (5/5) • Wait for the programming to finish • Try again if it fails

  12. SOFTWARE CONFIGURATION

  13. 1-D IDCT • A DCT is a Fourier-related transform similar to the discrete Fourier transform (DFT), but using only real numbers • We use Chen’s algorithm [*] for our 8-point IDCT design [*] W. H. Chen, C. H. Smith, and S. C. Fralick, “A fast computational algorithm for the discrete cosine transform,” IEEE Trans. Commun., Vol. COM-25, pp. 1004-1009, Sept. 1977.

  14. 2-D IDCT • 2-D IDCT is a separable transform, thus it can be computed by two passes of 1-D IDCT • First, compute row-wise 1-D IDCT on the block • Then, compute column-wise 1-D IDCT on the 1-D row-transformed data • Let X be the input 8×8 block, Y be the transformed block, we have

  15. Lab SW: IDCT Testbench (1/2) • The IDCT testbench will perform 2000 iterations of DCT & IDCT • In each iteration, the program will first generate a 8x8 block of type short with pixel value ranging from -255 to 256, transform the block via sw_dct_2d(), and then transform the block back via sw_idct_2d() & hw_idct_2d() • Error will be calculated by comparing the two results of IDCT • In this lab, sw_idct_2d() and hw_idct_2d() are exactly the same, so the resulting error will be 0

  16. Lab SW: IDCT Testbench (2/2) • sw_idct_2d() uses a static array of type short as transpose memory /* row transform */ for (ptr = tmem, row = 0; row < 8; row++) { sw_idct_1d(ptr++, block+(row<<3), MODE_ROW); } /* column transform */ for (ptr = block, row = 0; row < 8; row++) { sw_idct_1d(ptr++, tmem+(row<<3), MODE_COL); }

  17. Build SW Application • The source code can be obtained from lab_pkg/lab1/sw • Modify the path for ECOSDIR in Makefile for your environment • This is the path where the eCos library is built • Under lab_pkg/lab1/sw, type “make” to build the application properly (generating idct.elf) • -D_VERBOSE_ flag in Makefile is for more detailed testbench information • You can remove it for cleaner output information

  18. GRMON (1/3) • Under the directory where you built your IDCT testbench application, type “grmon-eval -u -eth -ip 10.0.0.10” • -u: Debug mode will enable both reading and writing to the UART from the monitor console • -eth: Connect using ethernet • Try resetting the board if GRMON fails to connect to your FPGA Press the RESET button

  19. GRMON (2/3) • You can use “info sys” to check for system configuration and memory mapping

  20. GRMON (3/3) • Type “load ./idct.elf” to load the program just built • Type “run” to run the program after loading • The results can be seen from the monitor • Press CTRL+c to exit the program

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