1 / 16

Threats and Challenges in FPGA Security

Threats and Challenges in FPGA Security. Ted Huffmire Naval Postgraduate School December 10, 2008. Overview. Problem Areas. Foundry Trust. Physical Attacks. Design Tools. Design Theft. System Assurance. Attacks. Trojan horse Backdoor Kill switch. Probing Sand and Scan

jillian-erickson
Download Presentation

Threats and Challenges in FPGA Security

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Threats and Challenges in FPGA Security Ted Huffmire Naval Postgraduate School December 10, 2008

  2. Overview Problem Areas Foundry Trust Physical Attacks Design Tools Design Theft System Assurance Attacks Trojan horse Backdoor Kill switch Probing Sand and Scan Side Channels Data Remanence Covert channels Side channels Bypass Cloning Reverse engineer Readback attack DoS Authentication Complex designs Solutions Trusted foundries FPGAs X-Ray Inspection Sand and Scan Tamper sensing Adding noise Degaussing Logical isolation Tracing wires Sanitization Continuous power Encrypt bitstream Watermarking Authentication Reference monitor Defense in depth User training Security usability Future Research All of supply chain Lessons from S/W Red teams Side channels Trusted tools Verification Languages CM High-assurance Partial reconfig PUFs High-assurance CMPs Tagging Dynamic security

  3. DRAM DRAM Reference Monitor DRAM DRAM DRAM DRAM CPU Core DRAM DRAM μP DRAM DRAM DRAM DRAM AES Crypto Core CPU Core SDRAM (off-chip) μP FPGA Chip Reconfigurable Hardware

  4. Reconfigurable Protection Separation Kernels Separate Processors app1 app2 app3 ReferenceMonitor app1 DRAM gate keeper gate keeper gate keeper kernel DRAM app2 DRAM app2 app1 app3 DRAM DRAM app3 DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Physical Software Spatial Temporal Protection Alternatives

  5. Design Flows

  6. Intertwined Cores

  7. DRAM DRAM Reference Monitor DRAM DRAM DRAM DRAM CPU Core DRAM DRAM DRAM DRAM DRAM DRAM AES AES Crypto Core CPU Core SDRAM (off-chip) FPGA Chip Moats

  8. Moats 1.0

  9. Moats 2.0

  10. Moats and Drawbridges

  11. DRAM DRAM Reference Monitor DRAM DRAM DRAM DRAM CPU Core DRAM DRAM μP DRAM DRAM DRAM DRAM AES Crypto Core X X CPU Core SDRAM (off-chip) μP FPGA Chip Interconnect Tracing

  12. DRAM DRAM Arbiter/Reference Monitor DRAM DRAM DRAM DRAM CPU Core DRAM DRAM μP DRAM DRAM DRAM DRAM AES Crypto Core CPU Core SDRAM (off-chip) μP FPGA Chip Communication Architecture

  13. DRAM DRAM Reference Monitor DRAM DRAM DRAM DRAM Reference Monitor CPU Core DRAM DRAM DRAM DRAM DRAM DRAM AES AES Crypto Core X CPU Core X SDRAM (off-chip) FPGA Chip Memory Protection

  14. Policy Compiler

  15. SoC Application

  16. Questions? • http://faculty.nps.edu/tdhuffmi

More Related