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4 bit Gray Code

4 bit Gray Code. Tejas Shah Joseph C. Chung Scott Tarkul Advisor: Dr. David Parent December 6, 2004. Agenda. Abstract Introduction Why 4-bit gray code? Theory of 4-bit gray code encoder/decoder Background Information Summary of Results Project (Experimental) Details Results

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4 bit Gray Code

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  1. 4 bit Gray Code Tejas Shah Joseph C. Chung Scott Tarkul Advisor: Dr. David Parent December 6, 2004

  2. Agenda • Abstract • Introduction • Why 4-bit gray code? • Theory of 4-bit gray code encoder/decoder • Background Information • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • Target spec • D Flip Flop additional logic used • 200Mhz clock frequency • Within 800x800μm2area • Power density spec of 23W/cm2 • Actual • D Flip Flop, XOR and MUX logic used • >200MHz of clock frequency • 8mW of Power • area of 250x150mm2

  4. Introduction • Create code that changes only 1 bit when counting • Example- (decimal) 5 (binary) 0101 (Gray code) 0111 6 0110 0101 • Greatly reduces error for counter processes • Encoding: show the Binary to Gray code conversion. A3A2A1A0 (A3)(A3+A2) (A2+A1) (A1+A0) • 0 1 1 0 (Binary)  010 1 • Decoding: Show the Gray to Binary code conversion. A3A2A1A0 (A3)(A3+A2)(A3+..A1)(A3+..A0) • 0 1 0 1 (Gray)  0110

  5. Project Details • Binary to Gray and Gray to Binary • Uniform cell heights of 24.9 μm • 5 XOR gates • 2 MUX gates • For decoding (Mux_sel=1) and encoding selection (Mux_sel=0) • 9 D-Flip Flops

  6. Longest Path Calculations Note: All widths are in microns and capacitances in fF

  7. Schematic

  8. Layout

  9. Verification

  10. Simulations

  11. Simulations

  12. Cost Analysis • Time spent on each phase of project • verifying logic: 1 week • verifying timing: 2 weeks • Layout: 3 weeks • post extracted timing: 2 days

  13. Lessons Learned • Start Flip-flop earlier • Minimize cells widths • When troubleshooting power consumption: • measure the power for each component to focus on the problem

  14. Summary • Our circuit is within spec. • Clock > 200MHz • Area is 250x150mm2 • The circuit power is 8mW • We learned to master implementing a logic design into layout form • Future: • More compact • More bits

  15. Acknowledgements • Thanks to Cadence Design Systems for the VLSI lab. • Thanks to Synopsys for Software donation. • Thanks to Professor David Parent for your support. • Thanks to all the team members. • Thanks to San Jose State for letting us work for late hours.

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