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This work presents a system for identifying and replacing layout configurations susceptible to process issues, improving manufacturability-aware physical design. By representing process-hotspots with range patterns, layouts are analyzed for yield impact and correction priority, enhancing routing efficiency.
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Efficient Process-Hotspot Detection UsingRange Pattern Matching in Routing Stage Hailong Yao1 Subarna Sinha2 Charles Chiang2 Xianlong Hong1 Yici Cai1 1Department of Computer Science and Technology Tsinghua University, Beijing, P.R. China 2Synopsys ATG, Mountain View, CA This work is done during the author’s internship at Synopsys ATG
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Experimental Results • Conclusion
Motivation • Manufacturability-aware physical design is becoming a necessity • Certain layout configurations susceptible to stress and lithographic process fluctuations affect yield • Process-hotspots: layout configurations most susceptible to process issues • Remove process-hotspots and replace them with more yield-friendly configurations
Limitations of Recommended Rules • Fabs use design rules (like recommended rules) to represent process-hotspots • Limitations: • Some effects are non-local • Difficult to represent relationships between large group of non-neighboring objects with a small set of rules • Explosion of design rules slows down the router • DRC tools are being supplemented with accurate process simulators (for instance, for lithography)
Limitations of Process Models • Lida Huang, et al at DAC’04 [1] and J. Mitra, et al at DAC’05 [2] proposed embedding an aerial image simulator in the router to identify process-hotspots • Limitations: • Lack of knowledge of downstream steps and over-estimation of process-hotspots • Huge computational expense [1] L.-D. Huang and M. D. F. Wong, “Optical proximity correction (OPC)-friendly maze routing,” In DAC, pages 186–191, June 2004. [2] J. Mitra, P. Yu, and D. Z. Pan, “RADAR: Ret-aware detailed routing using fast lithography simulations,” In DAC, pages 369–372, June 2005.
Represent Process-hotspots with Patterns • A good representation of process-hotspots would be a 2D layout of rectangles, i.e. a pattern • Can be built off-line using test-structures or more accurate simulation tools • Process-hotspot detection during routing would complement current advances in yield enabling steps
Scattering Bar S2 S1 Un-OPC-able Un-SRAF-able Why Range Pattern? • Layouts/patterns are quite similar with minor variations • Exact pattern: multiple similar patterns • Range pattern: a group of “similar” layouts with allowable variations in length, width and/or spacing • Ranges on the pattern parameters enable compact representation S1S2
Process-hotspot Detection • Collaborate with a fab or in-house accurate simulation and mask synthesis flows to build range patterns • Score the patterns in the set based on yield impact • Scores can be used by the router to give higher priority during correction • Represent process-hotspots as a library of range patterns • Process-hotspot detection: find all the locations where the layout is identical to one of the patterns contained in a range pattern
Outline • Motivation • Range Patterns and Matching • Range Pattern Definitions • Layout Representation • Range Pattern Representation • Process-Hotspot Detection System • Experimental Results • Conclusion
Range Pattern Definitions • Range pattern: DRC-correct two-dimensional layout of rectangles with additional specifications: • Widths and lengths of the rectangles can vary within certain user-specified bounds • Spacings between pairs of rectangles can vary within certain user-specified bounds • Optimal widths and lengths of the rectangles and optimal spacings between pairs of rectangles can be specified • Constraints can be specified over linear combinations of the widths, lengths and spacings of the rectangles
Range Pattern Example • Range pattern Staircase with the following specifications: • Optimal width of each rectangle = 90 nm • Optimal spacing between adjacent rectangles = 90 nm • Range of width of all rectangles = (90, 150) nm • Range of spacing between adjacent rectangles = (90, 150) nm • Range of length of central rectangle = (200, 500) nm • Distance between the right edge of rectangle 1 and the left edge of rectangle 3 cannot exceed 50 nm • A range pattern contains a multitude of exact patterns Rectangle 1 Rectangle 2 Rectangle 3
Range Pattern Matching Problem • The Range Pattern Matching (RPM) problem: Given a layout and a range pattern, determine all occurrences of the range pattern in the layout and score these occurrences using the scoring mechanism for the range pattern
Outline • Motivation • Range Patterns and Matching • Range Pattern Definitions • Layout Representation • Range Pattern Representation • Process-Hotspot Detection System • Experimental Results • Conclusion
Layout Representation • Layout is represented by a two-dimensional matrix LN1N2 where L[i,j] = 0 or 1 (0 i < N1, 0 j < N2) • Conversion: If a rectangle overlaps a grid location, the value at that location is set to 1. Otherwise, it is set to 0 • Different grid sizes result in different layout matrix
Outline • Motivation • Range Patterns and Matching • Range Pattern Definitions • Layout Representation • Range Pattern Representation • Process-Hotspot Detection System • Experimental Results • Conclusion
Cutting-slice Representation • Horizontal (vertical) slice: 2D matrix where all the rows (columns) are equal • Fragment of a slice: sub-matrix where all the elements are equal • Cutting-slice: a set of horizontal (vertical) slices {S0, … , Sn-1} with the following specifications: • Adjacent slices are not equal, i.e. Si Si+1, 0 i < n-1 • Each slice Si is decomposed into fragments {Fi,0, … , Fi,m-1}, where Fi,j Fi,j+1, 0 j < m-1 • If applicable, optimal values are specified for the fragments in each slice and for the slices themselves • If applicable, ranges are specified for each slice and/or fragments within the slice • If applicable, constraints between different fragments and/or slices are specified as linear functions
Cutting-slice of Range Pattern Staircase • Totally 5 slices: S0,…,S4 • Fragments in the ith slice have the same width as Si • Fragment length and slice width can vary • Si: slice width Fi,j: fragment length • Item 6 translates to | F0,0 - F4,0 | 50 R1 R2 R3 • Optimal width of each rectangle = 90 nm • Optimal spacing between adjacent rectangles = 90 nm • Range of width of all rectangles = (90, 150) nm • Range of spacing between adjacent rectangles = (90, 150) nm • Range of length of central rectangle = (200, 500) nm • Distance between the right edge of rectangle 1 and the left edge of rectangle 3 cannot exceed 50 nm
S0 S1 S2 S3 S4 S0 S1 S2 S3 S4 S0 S1 S2 S0 S1 S3 S4 S2 S3 Slicing Direction • Slicing direction: direction used to generate the slices • Slicing direction affects the number of cutting-slices • The total number of cutting-slices is calculated by enumerating all the range overlapping cases • Choose the slicing direction with less cutting-slices Staircase: slicing direction:V 3 cutting-slices slicing direction:H 1 cutting-slice
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Overview • Range Pattern Matching Sub-problem • Scalability and Runtime Optimization • Experimental Results • Conclusion
Overview • Hierarchical dual-grid scheme with matching done on two grid sizes • The grid sizes are used to generate the layout matrices and the cutting-slices of the range pattern • Matching with the coarse grid identifies locations that are potential matches • Match locations are verified on the finer grid size • Fine grid size is equal to the manufacturing grid size
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Overview • Range Pattern Matching Sub-problem • Scalability and Runtime Optimization • Experimental Results • Conclusion
Worm-like Movement of the Layout Block • Matching is done block by block • Layout matrix: L[N1][N2], Block: B[h][N2], where min h max • min (max): the minimum (maximum) possible number of rows of the range pattern • Enumerate all the blocks whose heights are between min and max on each row of the layout matrix • Worm-like enumeration: only the top and the bottom rows are changed each time to reuse work done in encoding the previous block • Enables incremental encoding and greatly improves runtime max min max min
KMP-based Filter • Basic idea: Encode both the block B and the cutting-slice C as 1D strings BE and CE, respectively. Search CE in BE to find all potential matches. All locations that are not matches are filtered out. The potential matches are examined more closely • The run-length compression of a column C[j][N] is equal to {b0, b1, …, bn-1}, where • bi bi+1 (0 i < n-1) • C[j][N] can be represented as a concatenation of n segments, i.e. b0 repeated 0 times, b1 repeated 1 times, and so on • Example: 111001111011000011 is compressed to 13021401120412 • Binary encoding: with “1” added at the top to distinguish between “01” and “1”: 11010101 = 213
Matching Example N2 • Encode the slices in the cutting-slice: 1D string: {3, 5, 13, 5, 3} • Identify the slices in the block • Run-length compression on each slice and encode the slices: {2, 10, 10, 2, 3, 5, 13, 5, 3, 2, 10, 10, 2} • Search the encoded cutting-slice {3, 5, 13, 5, 3} in the encoded block by KMP string matching algorithm • Columns 5-14 of the block are examined more closely for a true match and the remaining locations are filtered out 1 1 1 1 1 1 0 0 1 1 h 0 1 1 1 10 10 2 2 3 13 2 10 5 5 3 10 2 3 5 5 3 13
Complexity Analysis of the RPM Algorithm • Layout matrix: L[N1][N2] , Layout block: B[h][N2] where min h max • Slice identification: O(N2) • Let the number of identified slices be s (1 s N2), run-length compression takes O(s U), where U is the average time for updating the run-length compression of each slice • Incremental binary encoding: O(s) • KMP string matching: O(s) • The verification process for each potential match: O(1) • RPM algorithm for one layout block: max(N2, sU) • Total number of different blocks in the layout matrix L[N1][N2] is less than (N1-min+1)(max-min+1) • Total time complexity: O(max(N2, sU) (N1-min+1) (max-min+1)) • Key factors: Size of the layout (N1,N2), the variation range in the height of the cutting-slice (min,max)
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Overview • Range Pattern Matching Sub-problem • Scalability and Runtime Optimization • Experimental Results • Conclusion
Scalability and Runtime Optimization • Scalability: window-by-window matching • Consecutive windows overlap to avoid loss of matches • Runtime: matching on a fine grid size is slow • Hierarchical matching strategy: dual grid matching scheme of coarse grid matching followed by fine grid matching
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Experimental Results • Conclusion
Experimental Results • Platform: Linux 2.4 system, two 2.2 GHz CPUs, 2 GB RAM (only a single CPU used) • Totally 5 layouts: D1, D2, D3: metal layers of 0.60.6 mm2 design; D4, D5: metal layers of 1.81.8 mm2 design. All are 65 nm designs • The process-hotspot library:
Discussion • Maximum memory used is about 21MB • Hierarchical matching runs from a few seconds to 6 minutes • Can be embedded in the router to detect process-hotspots • Identified process-hotspots can be eliminated by local wire-spreading and/or widening • Rip up and reroute with new DRC rules based on the constraints of the range pattern
Outline • Motivation • Range Patterns and Matching • Process-Hotspot Detection System • Experimental Results • Conclusion
Conclusion • Represent process-hotspots as range patterns • Propose range pattern matching problem and algorithm • Process-hotspot detection system developed to find and score process-hotspots in a given layout • Scalable and fast, can work on large layouts, practical for efficiently detecting process-hotspots during routing • Future work: • Handle range patterns with “don’t care” regions • Algorithmic process-hotspot correction scheme • Combination with recommended rules to reduce the runtime burden on routers • More thorough comparisons with model-based approaches