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Design of a Diversified Router: Dedicated CRF + IPv4 Metarouter

This document discusses the design details of a diversified router with a dedicated CRF and IPv4 Metarouter. It covers the revision history, slide organization, logical and physical formats, and functionality of each block.

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Design of a Diversified Router: Dedicated CRF + IPv4 Metarouter

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  1. Design of aDiversified Router:Dedicated CRFplus IPv4 Metarouter John DeHartjdd@arl.wustl.edu http://www.arl.wustl.edu/arl

  2. Revision History • 5/22/06 (JDD): • Created • Buffer descriptor stuff probably needs updating. • 6/1/06 (JDD): • Updating data going between blocks, still in progress. • 6/2/06 (JDD): • More cleanup of data going between blocks. • Buffer descriptor details still need updating. • 6/5/06 (JDD): • Slight change to format for Lookup Key and defining what goes in each word in the NN ring. • Add IP Pkt Length to data Demux passes to Parse • 6/6/06 (JDD): • Reorganized the Lookup Result given to Hdr Format to distinguish between MR portion and Substrate portion. • Clean up labeling of data to Parse (MN vs. IP Pkt) • Output from Parse is still IP Pkt Offset and Length. • Data from Parse to Lookup needs update to reflect case where lookup is just for Substrate mapping of MI to LC. • 6/7/06 (JDD): • Updated notes about Parse block’s input/output and functionality • 6/15/06 (JDD): • Removed CRC from Rx to Demux data. • MSF does not pass us a CRC like we thought so we will skip the CRC checking. • Updated data going from Demux to Parse, Parse to Lookup and Lookup to Hdr Format

  3. Revision History • 6/19/06 (BDH): • Split Header Format into MR Header Format and Substrate Encap • Demux is now Substrate Decap • Reorganization of all slides into logical and physical formats, coloring scheme • IPv4 MR now has own section, integrated JL’s internal format slides

  4. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Dedicated CRF Slide Organization Metarouter Block Input Data Output Data Substrate • In the “at-a-glance” format, all blocks are logical • Logical inputs and outputs • High-level overview of processing • Each logical block is like an Intel microblock not necessarily an ME. • In the detailed format, all blocks are physical • Physical inputs and outputs • Specific functionality and implementation notes • Color scheme • Blue = Substrate, should not change! • Green = Metarouter, different for each MR

  5. Logical Formats

  6. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Receive Rx Buffer Handle RBUF Ethernet Frame Len Port • Coordinate transfer of packets from RBUF to DRAM

  7. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Substrate Decapsulate Buffer Handle Block Substrate Type Buffer Handle Src ID Ethernet Frame Len MN Frame Length Port MN Frame Offset • Read and validate Ethernet header from DRAM • Read and validate substrate header from DRAM • Extract Rx MI or Source MPE • Calculate MN frame length and offset

  8. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Metarouter Parse Buffer Handle Buffer Handle Lookup Flags MR Parse Parse Flags to Lookup Lookup Key Src ID (RxMI/SrcMPE) Src ID MN Frame Length MN Pkt Length MN Frame Offset to MR Hdr Format MR Data • Read and align MN header (includes IPv4 Hdr) from DRAM • MR-specific • Consume internal header (if packet from other MPE of MR) • Header validation • Header modification • Exception checks • Extract lookup key and set lookup flags • Write aligned modified IPv4 header back to DRAM

  9. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Lookup Buffer Handle Buffer Handle Lookup Result Flags Lookup Lookup Input Flags Dest Addr Lookup Key Output Port Src ID QID MN Pkt Length MR Lookup Result • Perform lookup in TCAM • Increment counters based on Stats Index • Priority resolution of results from multiple databases, if needed

  10. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Metarouter Header Format Buffer Handle Buffer Handle MN Frame Length Lookup Result Flags MR Hdr Format MN Frame Offset Dest Addr from Lookup Dest Addr Output Port QID Output Port QID MR Lookup Result • Process Lookup result • For exceptions, generate internal header • Decide substrate type Substrate Type from MR Parse MR Data Substr. Type-dep. Data

  11. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Substrate Encapsulation Buffer Handle MN Frame Length Buffer Handle Substr Encap MN Frame Offset Output Port Dest Addr QID Output Port MN Frame Length QID • Write substrate and ethernet headers Substrate Type Substr. Type-dep. Data

  12. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Queue Manager Buffer Handle QM Buffer Handle Output Port QID Output Port MN Frame Length • CRF queue management for Meta Interface queues • WRR? • Details

  13. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM Transmit Tx Buffer Handle TBUF Output Port • Coordinate transfer of packets from DRAM to TBUFs • Recycle buffer handle

  14. Physical Formats

  15. Buffer Descriptor Buf Handle(32b) Buffer_Next Eth. Frame Len (16b) Reserved (8b) Port (8b) Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Receive RBUF • RBUF format details here • Buf Handle details here • Notes: • We’ll pass the Buffer Handle which contains the SRAM address of the buffer descriptor. • From the SRAM address of the descriptor we can calculate the DRAM address of the buffer data.

  16. Buf Handle(32b) Buffer Descriptor Eth. Frame Len (16b) Reserved (8b) Port (8b) Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Substrate Decapsulate Buf Handle(32b) P Flags (4b) MR ID (VLAN) (12b) Rx MI(16b) MN Frm Length(16b) MN Frm Offset (16b) • P Flags: indicate RxMI vs. SrcMPE • bit0: 0: RxMI , 1: ScrMPE

  17. Buffer Descriptor Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Metarouter Parse Buf Handle(32b) Buf Handle(32b) L Flags (4b) MR Passthrough (28b) P Flags (4b) MR ID (VLAN) (12b) RxMI/SrcMPE (16b) MR Passthrough (32b) MN Pkt Length (16b) MN Pkt Offset (16b) Lookup Key[143-112] MR/MI (32b) Lookup Key[111-80] (32b) Lookup Key[ 79-48] (32b) Lookup Key[ 47-16] (32b) Lookup Key [15- 0] (16b) Reserved (16b) • L Flags: • bit 0: 0: Normal, 1: Substrate Lookup • bit 1: 0: Normal, 1: NH MN Address present in Key Word[1] • Key Word[0] = MR/MI • Bit 1 should never be set without bit 0 also being set. • Hdr Format needs to start at the beginning of the IP Header and re-write headers upward in the Buffer. • Can Parse adjust the buffer/packet size and offset? • Can Parse do something like, terminate a tunnel and strip off an outer header? • Rx MI needs to be passed to Header Format (through Lookup) so that Header Format can include it in the shim of packets that end up on the slow path. This will allow the Control Processor know what interface the exception packets arrived on.

  18. Buffer Descriptor Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Lookup Buf Handle(32b) Buf Handle(32b) H Flags (4b) MR Passthrough (28b) L Flags (4b) MR Passthrough (28b) MR Passthrough (32b) MR Passthrough (32b) Lookup Key[143-112] MR/MI (32b) MR Lookup Result (32b) Lookup Key[111-80] (32b) MR Lookup Result (32b) Lookup Key[ 79-48] (32b) Lookup Key[ 47-16] (32b) DA(8b) Port (4b) QID(20b) Lookup Key [15- 0] (16b) Reserved (16b) • L Flags: • bit 0: 0: Normal, 1: Substrate Lookup • bit 1: 0: Normal, 1: NH MN Address present in Key Word[1] • Key Word[0] = MR/MI • Bit 1 should never be set without bit 0 also being set.

  19. Buffer Descriptor Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Metarouter Header Format Buffer Handle(32b) Buf Handle(32b) H Flags (4b) MR Passthrough (28b) QID(20b) Port(8b) Rsv (4b) MR Passthrough (32b) MN Pkt Offset (8b) MN Pkt Length (16b) MR Lookup Result (32b) Rsv(16b) SH Type (8b) SH Len (8b) MR Lookup Result (32b) DA(8b) Port (4b) QID(20b) Substrate Header Data (LWO) Substrate Header Data (LW1) Substrate HeaderData (LW2) • Text Substrate Header Data (LW3) Substrate Header Data (LW4)

  20. Buffer Handle(32b) QID(20b) Port(8b) Rsv (4b) Buffer Descriptor Reserved (16b) MN Pkt Length (16b) Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Substrate Encapsulation Buffer Handle(32b) QID(20b) Port(8b) Rsv (4b) MN Pkt Offset (8b) MN Pkt Length (16b) Rsv(16b) SH Type (8b) SH Len (8b) Substrate Header Data (LWO) Substrate Header Data (LW1) Substrate HeaderData (LW2) Substrate Header Data (LW3) Substrate Header Data (LW4) • Substrate header types/formats here?

  21. Buffer Handle(32b) Buffer Handle(32b) QID(20b) Port(8b) Rsv (4b) Reserved (24b) Port(8b) Buffer Descriptor Reserved (16b) MN Pkt Length (16b) Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Queue Manager • Text

  22. Buffer Handle(32b) Reserved (24b) Port(8b) Buffer Descriptor Buffer_Next Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Transmit TBUF • Text

  23. IPv4 Metarouter MR Parse and MR Header Format Logical and Physical Data Formats

  24. MR Parse Lookup MR Hdr Format IPv4 Logical Formats Exception Bits Rx MI / Source MPE MN Frame Length MN Frame Offset Buffer Handle Buffer Handle Buffer Handle Buffer Handle Parse Flags Lookup Flags Lookup Result Flags MN Frame Length Rx MI / Source MPE Lookup Key Dest Addr MN Frame Offset MN Frame Length Rx MI / Tx MI Output Port Dest Addr QID MN Frame Offset Output Port IPv4 Lookup Flags QID TxMI Substrate Type IPv4 Lookup Result Substr. Type-dep. Data

  25. Buf Handle(32b) Buffer Handle(32b) P Flags (4b) MR ID (VLAN) (12b) RxMI/SrcMPE (16b) QID(20b) Port(8b) Rsv (4b) MN Pkt Length (16b) MN Pkt Offset (16b) Reserved (16b) IP Pkt Length (16b) MR Parse Lookup MR Hdr Format H (1b) D (1b) Buf Handle(32b) Buf Handle(32b) L Flags (4b) Exception Bits (12b) Rx MI/SrcMPE (16b) H Flags (4b) Exception Bits (12b) Rx MI/SrcMPE (16b) IP Pkt Length (16b) IP Pkt Offset (16b) IP Pkt Length (16b) IP Pkt Offset (16b) Lookup Key[143-112] MR/MI (32b) Lookup Key[111-80] DA (32b) N H (1b) Reserved (11b) L D (1b) TxMI(16b) M A C (1b) Lookup Key[ 79-48] SA (32b) MrBits[31:0](32b) Lookup Key[ 47-16] Ports (32b) Reserved (16b) Lookup Key Proto/TCP_Flags [15- 0] (16b) DA(8b) Port (4b) QID(20b) IPv4 Physical Formats H: Hit D: Drop

  26. IPv4 Parse and Header Format • Parse • Consume internal header • Verify IP header (per RFC1812 5.2.2) • Decrement TTL • Recalc IP checksum • Write updated checksum to DRAM • Store drop/exception/pass statistics • Extract lookup key, set lookup flags • Header Format

  27. IPv4 Flag Formats • IPv4 Lookup Flags • H: Hit • D: Drop • NH: NH MN Address present • MAC: MAC Address needed • LD: Local Delivery • IPv4 Exception Bits • Bit 0: TTL = 0 or 1 • Bit 1: Options • Bit 2?: RxMI or SrcMPE

  28. Type (1B) Length (1B) RxMI (2B) Type Dependent Data (2-6B) IPv4 Internal Header Formats • For packets going from IPv4 MPE to IPv4 MPE • Packets from Ingress LC or to Egress LC don’t have Metanet Internal Header

  29. IPv4 Internal Header Types • Packets entering routing MPE • Routing MPE: MPE that does routing lookup • FwdKey = [TxMI + MnNhAddr if multi-access link] (**)

  30. IPv4 Internal Header Types • Packets exiting Routing MPE • If FwdKey in MR Internal hdr is invalid, lookup raises error flag and hdr_fmt sends pkt to CMPE for debug (***)

  31. Extra • The next set of slides are for templates or extra information if needed

  32. Text Slide Template

  33. Image Slide Template

  34. L3 L3 L3 L1 L2 L2 L2 L1 Rx Substr Decap MR Parse Lookup MR Hdr Format Substr Encap Tx QM At-a-glance Block Template Block Buffer Handle RBUF Ethernet Frame Len Port • Text

  35. Buffer Descriptor Buf Handle(32b) Buffer_Next Eth. Frame Len (16b) Reserved (8b) Port (8b) Buffer_Size Offset Free_List Packet_Size MR_ID TxMI VLAN Packet_Next Detailed Block Template RBUF • Text

  36. Buffer Handle(32b) Buffer Handle(32b) MR-1 . . . QID(20b) Port(8b) Rsv (4b) Reserved (24b) Port(8b) MR-n Reserved (16b) IP Pkt Length (16b) QM/Scheduler on Multiple MEs Input Hlpr (1 ME) QM/Schd (1 ME) HeaderFormat Tx QM/Schd (1 ME) Tx NN/Scratch Rings NN Ring • QID(32b): • Reserved (8b) • QM ID (3b) • QID(17b): 1M queues per QM • Input Hlpr would use QM ID to select Scratch ring on which to put request. • QM/Sched then sends on its output NN/scratch ring to its associated Tx • With 64 entries in Q-Array and 16 entries in CAM, max number of QM/Schds is probably 4 (2 bits). • We’ll set aside 3 bits to give us flexibility in the future.

  37. Packet Buffer Descriptor Tradeoffs • Why use a Buffer Descriptor at all? • QM needs something to link packets/buffers in queues • ME-to-ME communications costs vs. SRAM access costs

  38. Packet Buffer Descriptor def • Meta Data structure of Packet Buffers (LSB to MSB) • buffer_next 32 bits Next Buffer Pointer (in a chain of buffers) • offset 16 bits Offset to start of data in bytes • BufferSize 16 bits Length of data in the current buffer in bytes • header_type 8 bits type of header at offset bytes in to the buffer • rx_stat 4 bits Receive status flags • free_list 4 bits Freelist ID • packet_size 16 bits (Total packet size across multiple buffers) • output_port 16 bits Output Port on the egress processor • input_port 16 bits Input Port on the ingress processor • nhid_type 4 bits Nexthop ID type. • reserved 4 bits Reserved • fabric_port 8 bits Output port for fabric indicating blade ID. • nexthop_id 16 bits NextHop IP ID • color 8 bits Qos Color • flow_id 24 bits QOS flow ID or MPLS label/flow id • reserved 16 bits Reserved • class_id 16 bits Class ID • packet_next 32 bits pointer to next packet (unused in cell mode)

  39. Packet Buffer Descriptor Gets • buffer_next: tx • Offset: rx, tx, fwd • BufferSize: tx, fwd • header_type: tx, fwd • rx_stat: NONE • free_listpacket_size: NONE • output_port: qm(?), tx • input_port: rx, fwd • nhid_type: NONE • fabric_port: qm(?), tx • nexthop_id • color • flow_id • class_id • packet_next

  40. Meta Data Caching • Meta Data can be cached in one of three places: • SRAM Xfer Registers • DRAM Xfer Registers • GPR Registers • Size of Meta Data Cache is controlled by #define META_CACHE_SIZE • Macro dl_meta_load_cache[] loads meta data cache • buffer_handle: buffer handle for which meta data is to be fetched • dl_meta: read transfer register prefix • Xbuf_alloc[] should be used to allocate the needed registers • signal_number: • START_LW: starting long word for fetch • NUM_LW: number of long words to fetch • Each microengine (microblock?) can use Meta Data Caching differently.

  41. Meta Data Caching • In the ipv4_v6_forwarder sample app, • dl_meta_load_cache() used in: • Egress • ethernet_arp.uc • pkt_tx_16p.uc • statistics_util.uc • tx_helper.uc • Ingress • ethernet_arp.uc • pkt_tx_16p.uc • statistics_util.uc • tx_helper.uc • dl_meta_get_*[] used in: • Egress • ethernet_arp.uc • pkt_tx_16p.uc • tx_helper.uc • Ingress • Ether.uc • Ipv4_fwder.uc • Ipv4_fwder_util.uc • Ipv6_fwder.uc • V6v4_tunnel_decap.uc • V6v4_tunnel_encap.uc • pkt_tx_16p.uc • tx_helper.uc • dl_meta_set_*[] used in: • Egress • ethernet_arp.uc • pkt_rx_init.uc • pkt_rx_two_me_util.uc • Ingress • pkt_rx_init.uc • pkt_rx_two_me_util.uc • Ether.uc • Ipv4_fwder_util.uc • Ipv6_fwder.uc • V6v4_tunnel_decap.uc • V6v4_tunnel_encap.uc • pkt_tx_16p.uc • tx_helper.uc

  42. Buffer Handle

  43. Buffer Descriptor Usage • Is there a different Buffer Descriptor defn for LC and PE? • Will we support Multi-Buffer Packets? • If not, we do not need buffer_next(32b) or buffer_size(16b) • QM uses packet_next for its packet chaining in qarray. • Output Port and Input Port probably translate to TxMI and RxMI • Next Hop fields (nhid_type(4b) and nexthop_id(16b)) probably can go away. • QOS fields (color(8b) and flow_id(24b)) probably can go away. • Two reserved fields 4b and 16b can go away. • class_id(16b) (virtual queue id?) can probably go away. • fabric_port can probably go away.

  44. Buffer Descriptor Usage • PE Buffer Descriptor: • MR_ID (16b) • TxMI (16b) • VLAN (16b) • buffer_next 32 bits Next Buffer Pointer (in a chain of buffers) • offset 16 bits Offset to start of data in bytes • BufferSize 16 bits Length of data in the current buffer in bytes • header_type 8 bits type of header at offset bytes in to the buffer • rx_stat 4 bits Receive status flags • free_list 4 bits Freelist ID • packet_size 16 bits (Total packet size across multiple buffers) • output_port 16 bits Output Port on the egress processor • input_port 16 bits Input Port on the ingress processor • nhid_type 4 bits Nexthop ID type. • reserved 4 bits Reserved • fabric_port 8 bits Output port for fabric indicating blade ID. • nexthop_id 16 bits NextHop IP ID • color 8 bits Qos Color • flow_id 24 bits QOS flow ID or MPLS label/flow id • reserved 16 bits Reserved • class_id 16 bits Class ID • packet_next 32 bits pointer to next packet (unused in cell mode)

  45. Buffer Descriptor Usage • PE Buffer Descriptor: • LW0: buffer_next 32 bits Next Buffer Pointer (in a chain of buffers) • LW1: offset 16 bits Offset to start of data in bytes • LW1: BufferSize 16 bits Length of data in the current buffer in bytes • LW2: reserved 8 bits reserved/unused • LW2: reserved 4 bits reserved/unused • LW2: free_list 4 bits Freelist ID • LW2: packet_size 16 bits (Total packet size across multiple buffers) • LW3: MR_ID 16 bits Meta Router ID • LW3: TxMI 16 bits Transmit Meta Interface • LW4: VLAN 16 bits VLAN • LW4: reserved 16 bits reserved/unused • LW5: reserved 32 bits reserved/unused • LW6: reserved 32 bits reserved/unused • LW7: packet_next 32 bits pointer to next packet (unused in cell mode) • Leave multi-buffer fields there as a template for the dedicated blade implementation of a jumbo-frame MR. • Also reduces changes to Rx, Tx, and QM and reduces potential problems.

  46. Multicast Alternatives • At least Three Options • Force MRs that need Multicast to be Dedicated Blade MRs and do their own Multicast • For our short term goals this is probably sufficient and the best course. • Perhaps longer term we can look at adding it to the CRF • Treat as exception and send to Xscale • Provide support in CRF for Multicast • Use Multi-Hit Lookup capability of the TCAM • MI Bit mask defined in Lookup Result • Will put a bound on the number of MIs that can be supported on an MR because of the size of the lookup result. • Has issues of mapping bits in the bit mask to actual MIs. • Lookup Result contains an index into a table containing MI bit masks • Allow but do not force MRs to provide code to interpret Lookup Result. • This would also allow other possible extensions on an MR-specific basis • This carries with it the problem of bounding the execution time of the MR-specific code in the Lookup block. For general multicast, this could be a serious issue. • There are also issues with generating a QID based on an MI when the QID is not included in the Lookup Result. • Other options?

  47. MR-1 . . . MR-n DRAM Buf Ptr DRAM Buf Ptr DRAM Buf Ptr MR Id DRAM Buf Ptr MR Id MR Id Output MI MR Id Input MI Output MI MR Lookup Key MR Ctrl Blk Ptr MR Ctrl Blk Ptr QID MR Ctrl Blk Ptr MR Mem Ptr MR Mem Ptr Buffer Offset QID MR Mem Ptr Stats Index MR Specific Lookup Result CRF Support for Multicast Default/Unicast path MR Interp HeaderFormat Parse MR-Specific Path Post Process Lookup MR-1 . . . MR-n

  48. DRAM Buf Ptr DRAM Buf Ptr MR Id MR Id Output MI Output MI Copy Cnt=1 Copy Cnt MR Ctrl Blk Ptr MR Ctrl Blk Ptr MR Mem Ptr MR Mem Ptr QID QID Stats Index Stats Index MR Specific Lookup Result MR Specific Lookup Result CRF Support for Multicast Default path MR Interp MR-Specific Path Post Process Lookup DRAM Buf Ptr MR Id MR Lookup Key • We will need some kind of copy count or multicast bit and last copy bit to let TX know when it can release the DRAM buffer that holds the packet. MR Ctrl Blk Ptr MR Mem Ptr

  49. DRAM Buf Ptr DRAM Buf Ptr DRAM Buf Ptr MR Id MR Id MR Id Output MI Output MI Output MI Output MI Output MI Copy Cnt Output MI Copy Cnt Copy Cnt Copy Cnt Copy Cnt Copy Cnt MR Ctrl Blk Ptr MR Ctrl Blk Ptr MR Ctrl Blk Ptr MR Mem Ptr MR Mem Ptr MR Mem Ptr QID QID QID Stats Index Stats Index Stats Index MR Specific Lookup Result MR Specific Lookup Result MR Specific Lookup Result CRF Support for Multicast Default path MR Interp MR-Specific Path Post Process Lookup DRAM Buf Ptr DRAM Buf Ptr MR Id MR Lookup Key • We will need some kind of copy count or multicast bit and last copy bit to let TX know when it can release the DRAM buffer that holds the packet. MR Lookup Key MR Specific Lookup Result MR Ctrl Blk Ptr MR Ctrl Blk Ptr MR Mem Ptr MR Mem Ptr

  50. OLD • The rest of these are old slides that should be deleted at some point.

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