Multiplexer and Bus-Based Transfers for Multiple Registers

1. Multiplexer and Bus-Based Transfers for Multiple Registers ~ Outline ~ • Multiplexer-based transfers • Dedicated Multiplexers – based transfer • Multiplexer Bus (Single Bus)

2. Multiplexer-Based Transfers • Implement one or more microoperations with a single register as the destination of all primary results. • The single register may also serve as a source of an operand for binary and unary operations. • A dedicated multiplexer is used to select the wanted input. • A simple technique using multiplexers for selection is introduced to allow multiple microoperations on a single register. • Multiplexers and parallel load registers can be used to implement dedicated transfers from multiple sources.

3. Multiplexer-Based Transfers • A register receives data transfers from more than 1 sources. • A dedicated multiplexer is used to select the wanted input. • Example shows: • If K1=1: R0 receives data from R1. • If K1=0: R0 receives data from R2. K2 K1 R2 n=4 Load S R0 0 1 n=4 R1 2:1 MUX n=4

4. Multiplexer-Based Transfers • How do we represent this in RTL form? • Written in if-then-else: If (K1=1) then (R0 R1), else if (K2=1) then (R0 R2). • Written in RTL: K2 K1 R2 n=4 Load S R0 K1:R0 R1, K1K2:R0 R2 0 1 n=4 R1 2:1 MUX n=4 Hardware connections from two source registers, R1 and R2, to one common destination register, R0. Selection between R1 and R2 must be based on the control variables K1 and K2.

5. Analyse the diagram for input: *n.c : no change Multiplexer-Based Transfers K2 K1 R2 n=4 Load S R0 0 1 n=4 R1 2:1 MUX n=4

6. K2 K1 Load K2 K1 2 to 1 MUX Load D0 D1 D2 D3 Q0 Q1 Q2 Q3 R2 R2 S Block Diagram n=4 A0 A1 A2 A3 Load S R0 R0 0 Q0 Q1 Q2 Q3 Y0 Y1 Y2 Y3 Load 1 n=4 B0 B1 B2 B3 R1 2:1 MUX CLK n=4 Q0 Q1 Q2 Q3 D0 D1 D2 D3 D0 D1 D2 D3 R1 Detailed Logic Multiplexer-Based Transfers Transforming a Block Diagram into Detailed Logic

7. L2 S2 S1 L0 L1 S0 LOAD SELECT MUX0 Dedicated MUX – based Transfer • Three n-bit 2:1 MUX, each with its own SELECT signal MUX0 : S0; MUX1 : S1; MUX2 : S2 • Each register has its own LOAD signal R0 : L0; R1 : L1; R2 : L2 • Multiplexer connected to each register input produces a very flexible structure • Characterize the simultaneous transfers possible with this structure. MUX1 MUX2

8. Example 1: L2 : R2 ← R1 S0, S1, S2 = (0,0,1) and L0, L1, L2 = (0,0,1) then L2 : R2 ← R1

9. Example 2: L1: R1 ← R0, L2 : R2← R0 S0, S1, S2 = (1,0,0) and L0, L1, L2 = (0,1,1) then L1: R1 ← R0, L2 : R2← R0

10. Dedicated Multiplexers vs. Multiplexer Bus • A typical digital system has many registers. • Paths must be provided to transfer data from one register to another. • Multiplexer dedicated to each register has problems: • Excessive amount of logic • High number of interconnections

11. Dedicated Multiplexers vs. Multiplexer Bus A more efficient system for transferring data between registers: • Use a shared transfer paths for registers • A shared transfer object is called a bus • A bus is characterized by a set of common lines, with each line driven by selection logic. • Control signals for the logic select a single source and one or more destinations on any clock cycle for which a transfer occurs.

12. Multiplexer Bus (Single Bus) • Bus implementation using : • Multiplexers • Three – state nodes and drivers • In most cases, the number of bits is the length of the receiving register • Only need a single n-bit 3:1 MUX and parallel load registers. • MUX outputs are shared as a common path (bus)

13. Multiplexer Bus (Single Bus) • SELECT signal • Determines the contents of single source register that will appear on the MUX outputs. S1S0 MUX Source.Reg 00 0 R0 01 1 R1 10 2 R2 • LOAD signal • Determine the destination register / registers to be loaded with the bus data 0 1 2

14. Multiplexer Bus Example 1: S1, S0 = (0,0) and L0, L1, L2 = (0,0,1) then L2 : R2 R0

15. Multiplexer Bus Example 2: S1, S0 = (1,0) and L0, L1, L2 = (1,1,0) then L0: R0 R2, L1 : R1 R2

16. Multiplexer Bus Example 3: S1, S0 = (1,0) and L0, L1, L2 = (0,1,1) then L1: R1 R2, L2 : R2 R2 (no change)

17. Multiplexer Bus • A single bus driven by a MUX lowers cost, but limits the available transfers • Characterize the simultaneous transfers possible with this structure… • Characterize the cost savings compared to dedicated MUX…

18. Multiplexer Bus • 3rd transfer : cannot be done • Requires 2 simultaneous sources (R0 and R1) on a single bus • Cannot occur in 1 clock cycle • This transfer requires at least 2 buses • However, dedicated MUX can do this transfer

19. MUX-based vs Bus-based • MUX-based • Any combination of transfers is possible • Bus-based • Simultaneous transfers from different sources in single clock cycle is impossible • Reduction in hardware • Limitation in simultaneous transfers

20. Three – State Bus • The 3 – input MUX can be replaced by a 3 – state node (bus) and 3 – state buffers • Cost is further reduced • Signals can travel in 2 directions • Use same bus to carry signals into and out of registers

21. Three – State Bus • LOAD signal L0 : R0; L1 : R1; L2 : R2 • ENABLE signal E0 : R0; E1 : R1; E2 : R2 • A register with n lines that serve as both inputs and outputs. • 3-state buffers are enabled: • The n lines are OUTPUTS. • 3-state buffers are disabled: • The n lines are INPUTS.

22. Multiplexer Bus Three – StateBus