EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Spring 2007Instructor: Dr. Michael FrankModule #14: Modular Sequential Design(Thanks to Dr. Perry for some slides)

2. Frequently-Used Modular Sequential Components • Memory elements: • Flip-flops & Registers (already covered) • Synchronous ROMs (w. registered I/O ports) • RAMs (asynchronous & synchronous) • Simple, common state machines: • Counters (plain binary and mod-n) • Accumulators • Shift registers (left/right, w. serial & parallel I/O)

3. Insert more slides here… • Most of the remaining slides in this module need to be deleted, and replaced with some slides giving examples of modular sequential designs of the above components, and explaining their functions…

4. Dr. Perry’s Slides Following are some old slides by Dr. Perry on Counters and Shift Registers, left over from previous semesters…

5. FSM Examples

6. Example– 2-bit Up Counter • State Diagram Clock is implied

7. Example – 2-bit Up Counter • State Table State Value Assignment Let Output Vector Let S0 = reset state

8. Example – 2-bit Up Counter • Truth Table

9. Example – 2-bit Up Counter • Excitation Equations

10. Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

11. Reg Block F Logic Y Vector H Logic Logic Diagram No X Vector in this Example No H Logic needed

12. Logic Diagram

13. Flash Animation

14. Example 3– 2-bit Down Counter • State Diagram Clock is implied

15. Example – 2-bit Down Counter • State Table Let Let S0 = reset state

16. Example – 2-bit Down Counter • Truth Table

17. Example – 2-bit Down Counter • Excitation Equations

18. Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

19. Logic Diagram Reg Block F Logic Y Vector H Logic No X Vector in this Example

20. Logic Diagram

21. Example 4 – 2-bit Up/Down Counter • State Diagram

22. Example – 2-bit Up/Down Counter • State Diagram Shorthand Notation

23. Example – 2-bit Up/Down Counter • State Table Let Let S0 = reset state

24. Example – 2-bit Up/Down Counter • Truth Table

25. Example – 2-bit Up/Down Counter • Excitation Equations

26. Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

27. Logic Diagram Reg Block X Vector F Logic Y Vector H Logic

28. Logic Diagram

29. Example 5– 3-bit Arbitrary Counter • Design a 3-bit arbitrary counter that will count in the following sequence 3,2,3,1,2,3 If a state is not used reset it to state zero. • How may states do we have? • How many registers do we need? • How many bits do we need for Y?

30. Example 5– 3-bit Arbitrary Counter • State Diagram

31. Example – Arbitrary 3-bit Counter Assign State Values • State Table Let Let S0 = reset state

32. Develop Truth Table

33. Example – 2-bit Arbitrary Counter • Develop Excitation Equations -- F Logic

34. Develop Excitation Equations for Y Y1 Y0

35. Example – 2-bit Arbitrary Counter • Excitation Equations -- H Logic

36. Recall Moore FSM Next State Present State Output Vector Input Vector Clock Feedback Path Reset State Equations

37. Logic Circuit H REG F

38. Logic Circuit

39. Simulation

40. Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET) • State Diagram Clock is implied

41. Example – 2-bit Up/Down Counter with Enable and SRESET • Functional Table Highest Level of Priority Lowest Level of Priority

42. State Table

43. Truth Table (5 variables!!) Although, we could design this circuit directly from the truth table we will use design partitioning.

44. Moore FSM Architecture Next State Present State Output Vector Input Vector Feedback Path

45. Partitioned Design We have srn en Note, with the partitioned design we can “reuse” already designed submodules to create the “new” design.

46. Top Level Block Diagram

47. UP/Down Logic Logic Circuit Symbol

48. Register Block Symbol Logic Circuit

49. 2 Bit 4x1 Mux Circuit Symbol

50. 1-bit 4x1 Mux Logic Circuit Symbol