Survey of Partial Scan Methodologies

1. Survey of Partial Scan Methodologies Zdeněk Kotásek Faculty of Information Technology Brno University of Technology Božetěchova 2 Brno, Czech Republic. E-mail:kotasek@fit.vutbr.cz http://www.fit.vutbr.cz/~kotasek/

2. Survey of Partial Scan Methodologies The outline of the presentation • The reasons for partial scan • Testability-based partial scan methodologies • Partial scan methodologies based on test generator usage • Partial scan methodologies based on the analysis of circuit structure • Our activities in the area of partial scan methodologies

3. The Reasons for Partial Scan • One possibility how to generate test for a sequential circuit is through automatic test pattern generation for sequential circuits (SATPG). • Automatic test pattern generation for sequential circuits (SATPG) is generally considered to be a hard problem. • Full scan design techniques attempt to alleviate this problem by connecting all flip-flops (FFs) or latches into a scan path during test mode so that all these elements become easily controllable and observable. • Thus, in a circuit designed using full scan the portion of the circuit excluding the scan path is fully combinational.

4. The Reasons for Partial Scan • Two reasons against the full-scan techniques exist: - the test application time associated with full-scan may be extremely high - the full scan may be prohibitively expensive due to high area overhead • The length of a test sequence for the full scan shift is L full scan = V x (N + 1) + N, where V is the number of test vectors, N is the number of scanned FFs

5. The Reasons for Partial Scan • The solution to the full scan costs - partial scan techniques. • The reduction of test application time - arranging scan flip-flops in parallel scan chains. • Partial scan techniques - only a subset of FFs are included into the scan path such that the remainder of the circuit has certain desirable testability properties. • The subset of FFs must be identified in some way, this goal is solved by partial scan methodologies.

6. The classification of partial scan methodologies • Partial scan methodologies can be classified into 3 groups of methodologies: - testability-based partial scan methodologies - partial scan methodologies based on test generator usage - partial scan methodologies based on the analysis of circuit structure

7. Testability-based partial scan methodologies Basic ideas: • These methods utilise usually gate level designs for the analysis. • The values representing controllability/observability factors of circuit nodes are computed, these values are then evaluated in a defined way. • The function used to do this can be seen as a global function reflecting diagnostic features of the circuit, namely controllability/observability. • Then, the circuit is modified, global functionevaluated again and the impact on testability factors investigated. • The modifications which effect the global function (testability) positively are then taken into account.

8. Testability-based partial scan methodologies • [PARI95] Parikh, P. S. - Abramovici, M.: Testability- Based Partial Scan Analysis, Journal of Electronic Testing: Theory and Applications, Vol. 7, 1995, No. 1/2, pp. 62 - 70 • The following parameters are computed: detectability cost of every line in the circuit (minimum number of clock cycles required to detect the fault). • 3 components of detectability cost of a line: controllability cost (activating the fault), sequential depth (propagating its fault effect), and enabling cost (sensitising the propagation path). • The result of applying the cost-based partial-scan (CoPS) algorithms - theidentification of FFs for the partial scan chain.

9. Testability-based partial scan methodologies Computation of Costs • Controllability. The controllability cost of line l for value v, denoted by Cv(l), is the minimum number of clock cycles required to set l to value v. Controllability computation for NAND gate output

10. Testability-based partial scan methodologies FF output controllability computations

11. Testability-based partial scan methodologies Controllability values for fanout situations

12. Testability-based partial scan methodologies • Sequential depth. The sequential depth of line l for a value v, denoted by Dv(l), is the number of FFs along path P between l and a PO, where P is the easiest path to propagate a v/ v effect from l to a PO (v is the value of l in the good circuit,and v is the value of l in the faulty circuit).

13. Testability-based partial scan methodologies Sequential depth computation for AND and NAND gates Sequential depth computation for FF

14. Testability-based partial scan methodologies • Enabling cost. Let P be the easiest path to propagate a fault effect v/v from l to a PO. The enabling cost of line l for a value v, denoted by Ev(l), is the maximum controllability cost required to enable the propagation of a fault effect v/v along P.

15. Testability-based partial scan methodologies Enabling cost computation for NAND gate

16. Testability-based partial scan methodologies Enabling cost computation for FF

17. Testability-based partial scan methodologies • Detectability. Let f be the fault l s-a-v. The detectability cost of fault f denoted by DET( f ), is the minimum number of cycles required to detect f. The detectability cost of a fault estimates the relative difficulty of detecting the fault. DET( f ) is computed by Det (F) = max {C v( l ), E v( l )} + D v( l ) • The detectability cost of a fault estimates the relative difficulty of detecting the fault.

18. Testability-based partial scan methodologies • The principle of sensitivity analysis - the proposed change to improve the testability of a circuit is not evaluated only by the improvement in the costs of the signals directly involved in that change, but by the improvement of the total function (TCF) of the circuit. The TCF is calculated by TCF=Σ DET( f ). f

19. Testability-based partial scan methodologies • The summation is performed for all targetfaults - the TCF can then be used as a measure of the relative difficulty of testing the circuit for the given set of faults. • Sensitivity. The sensitivity, ζ, is the change in the TCF value resulting from a change in the circuit (ζ = ΔTCF). In our case, the change is scanning a particular FF.

20. Testability-based partial scan methodologies The conclusions: • For this type of methodologies it is typical that the testability of the circuit under analysis is evaluated by means of a global function, a modification (a FF is included into the scan chain) is performed and the effect of the modification is evaluated. • Then, if the modification of the circuit has a positive effect on the global function value (testability has increased), the modification is accepted, otherwise it is refused. • These approaches are sometimes denoted as analytical approaches.

21. Partial scan methodologies based on test generator usage Basic ideas: • These methods utilise test generator (functional or structural test), then a methodology to identify FFs to be included into a scan register is used. • Agrawal, V. D. - Cheng, K. - Johnson, D. D. - Lin, T.: Designing Circuits with Partial Scan, IEEE Design & Test of Computers, April 1988, pp. 8 - 15 • In this methodology, functional test vectors are generated first. • Then, the faults in the combinational part of the circuit that are not detected by functional vectors are designated astarget faults for scan test generation.

22. Partial scan methodologies based on test generator usage • A typical feature of functional vectors - designer's primary aim is design verification and not the coverage of stuck-faults. • The fault coverage of functional tests - not be as high as required for manufacturing tests => it appears that functional vectors, augmented by scan vectors may be a reasonable solution to increase the quality of test. • The goal is to include the smallest possible number of FFs in the chain, and yet attain acceptable fault coverage.

23. Partial scan methodologies based on test generator usage • The concept of Option Table is introduced and utilised in the methodology. • The table consists of the coverage of target faults as a function of the number of FFs in the scan register, for every target fault it is determined how many test vectors are available to test particular fault and which FFs will be active. • An example: suppose the circuit contains 4 FFs (A, B, C and D), and there are 4 undetected faults. Table 1 shows the FF usage data.

24. Partial scan methodologies based on test generator usage • The concept of Option table

25. Partial scan methodologies based on test generator usage • The principle of generating the table: for each target fault, the set of tests is generated - then, for each test vector, FFs that must be manipulated are identified. • The entry “1” under ti1 in the above table means that the particular test uses no FF. • See the row 1 (fault F1) - the fault can be detected by two tests - the first one requires no FF to be active (set to a defined value), for the second one A and B FFs will be set. • The objective is to select, for a given number of FFs, a set of tests (one per fault) to cover the largest number of faults. This a set coverage problem.

26. Partial scan methodologies based on test generator usage Algorithm for FFs identification for partial scan chain Fault simulate entire circuit with functional vectors Generate list of undetected faults Fun Isolate combinational portion of circuit Map Fun onto combinational part to obtain target faults Fcomb Begin for every fi  Fcombgenerate all tests tij, j = 1, 2, … for fi End GenerateOption Table: Estimated fault coverage vs. FF usage Select an option from the Option Table In combinational model make unscanned FF I/O inaccessible

27. Partial scan methodologies based on test generator usage Begin For every vector generated for this option do Randomly fill unknown bits corresponding to scan FFs Fault simulate Fcomb Remove detected faults from Fcomb Generate test sequence End Add shift register test sequence

28. Partial scan methodologies based on test generator usage The conclusions: • In the methodology, functional test is generated first. • Then faults which are not detected by the functional test are identified by means of fault simulation process. • Option table is used to identify FFs which can be used to cover faults undetected by functional test (coverage problem). • These FFs are included into the scan chain.

29. Partial scan methodologies based on test generator usage • Higami, Y. - Kajihara, S. - Kinoshita, K.: Partial Scan Design and Test Sequence Generation Based on Reduced Scan Shift Method, Journal of Electronic Testing: Theory and Applications, Vol. 7, č.. 1/2, 1995, pp. 115 - 124 • The Partial scan algorithm was developed, called PARES - Partial scan Algorithm based on Reduced Scan shift.

30. Partial scan methodologies based on test generator usage Control and observation requirements st = (FFa,FFb, FFc) re = (FFa,FFb, FFc)

31. Partial scan methodologies based on test generator usage • NSO, NSC - the length of scan shift required for ith test vector tifor observing and controlling FFs. • Vector sti - partial scan vector of ti and includes values of scanned FFs. • X in vector sti means a don´t care value. • FFs with X are not required to be controlled. • Vector reishows whether fault effects of Fi are propagated to scanned FFs or not propagated by applying ti. • D in vector reimeans the propagation of fault effects => a FF with D is required to be observed.

32. Partial scan methodologies based on test generator usage • Test t1: FFa and FFb are required to be controlled, and only FFc is required to be observed in order to detect F1. • NSO, NSC for each test vector, when a scan chain is configured as FFa- FFb - FFc. • The required number of scan shift operations (for t1 - t2 - t3 sequence of tests): 2, 1, 2 before t1, t2, t3 1 after t3 application => 6 clock pulses + additional 3 clock pulses to apply every test t1, t2, t3 - altogether 9 clock pulses (partial scan).

33. Partial scan methodologies based on test generator usage • The solution for full scan: we have 3 test vectors to be applied into 3 FFs. Loading the test vectors into FFs is combined with reading (observing) the contents of FFs. As mentioned above: The length of a test sequence for the full scanshift (mentioned previously) is L full scan = V x (N + 1) + N, where V is the number of test vectors, N is the number of scanned FFs The number of clock pulses to be generated to apply the test in full scan - 15 clock pulses.

34. Partial scan methodologies based on test generator usage A method of selecting scanned FFs and their arrangement in a scan chain implemented in PARES • First step: test vectors are generated for the combinational part => FFs that must be controlled and FFs to which fault effects are propagated are found for each test vector. • Principle No. 1: Frequently controlled/observed FFs should be selected as scanned FFs. • Principle No. 2: FFs to be controlled for more test vectors are located close to the scan input. • Principle No. 3: FFs to be observed for more test vectors are located close to the scan output.

35. Partial scan methodologies based on test generator usage • The effect ofprinciples 1 - 3: required scan shift operations are expected to be small. • The measures Wpand Wm are calculated for each FF: Wp (FFi) = VC(FFi) + VO(FFi) Wm (FFi) = VC(FFi) - VO(FFi) VC(FFi) and VO(FFi) - the number of test vectors which require FFi to be controlled and observed • FFs having larger Wpare selected as a scanned FF. • FFs having larger Wmare located close to the scan input.

36. Partial scan methodologies based on test generator usage Example: • The task: the selection of three scanned FFs among five FFs. X: don‘t care, D: fault effect Table 2: control and observation requirements

37. Partial scan methodologies based on test generator usage • The explanation of symbols in Table 2: sti - partial vector of a test vector rei - vector which shows the propagation of fault effects • FFs with X (don’t care value) are not required to be controlled. • D means the propagation of a fault effects to FFs => FFs with D are required to be observed.

38. Partial scan methodologies based on test generator usage Table 3: VC, VO, Wp, Wm Consequences: the required number of scanned FFs = 3 => FFa, FFb, FFc are selected for scan (based on the largest Wpvalue ), in the order of FFc-FFb-FFa (according to Wm value).

39. Partial scan methodologies based on test generator usage • Consequences: on the basis of applying the methodology, some FFs are scanned, some are not scanned => for the unscanned FFs the clock signal must be inactive to hold the values of FFs. • The following figure - FF1, FF2, FF3 are scanned, FF4, FF5 are uncanned. • The mode control - normal operation/scan shift operation.

40. Partial scan methodologies based on test generator usage

41. Partial scan methodologies based on the analysis of circuit structure Basic ideas: These methods are based on the following steps: • Structure analysis of the circuit under design, • Identifying pathsand circuit structures through which diagnostic data (test vectors and responses to them) can be transferred (i. e. utilised for the test application) without any modifications, • Identifying elements in the circuit under design which can be tested through these structure, • Identifying elements which cannot be tested through the circuit structure - they must be included into the scan chain

42. Partial scan methodologies based on the analysis of circuit structure • [AbB85]Abadir, M. S. - Breuer, M. A.: A Knowledge Based System for Designing Testable VLSI chips, IEEE Design&Test, August 1985, pp. 56 - 68 • The concept of I path was introduced and utilised in the methodology: • Definition 1: A structure S with an input port X and an output port Y is said to have an identity mode (I - mode), denoted by M(S : X –> Y ), if S has a mode of operation in which the data on port X is transferred (possibly after clocking) to port Y.

43. Partial scan methodologies based on the analysis of circuit structure • Definition 2: There is an identity transfer path (I path) from output port X of structure S1 to input port Y of structure S2, denoted by P( S1:X –> S2:Y), if the data at port X can be transferred unchanged to port Y. • Every I path has a time tag and an activation plan. • Definitions 1 and 2 represent the concepts on which many methodologies were developed in the past and are still developed at present.

44. Partial scan methodologies based on the analysis of circuit structure • The transparency of elements to data loaded to their inputsand the transparency of data paths recognised in the circuit under analysis - the basic property which is evaluated during the testability analysis. • From this point of view two basic categories of elements can be recognised in an RTL circuit: data processors (DP) and data transporters (DT). • The role of registers - elements through which a test is applied => it is important to identify all registers in the circuit under analysis and assign a role they will cover during the test application.

45. Partial scan methodologies based on the analysis of circuit structure • Further results of the research team were published in GUPT95 - Gupta, R. - Breuer, M. A.: Partial Scan Design of Register-Transfer Level Circuits, Journal of Electronic Testing: Theory and Applications, Vol. 7, 1995, No. 1/2, pp. 25 - 46 • Basic idea: RTL designs generally consist of functional blocks and registers that are interconnected by multiplexers and buses to maximise resource sharing. • => the methodology is based on the identification of certain types of elements which may be important during the test application.

46. Partial scan methodologies based on the analysis of circuit structure • The concept of switches is introduced - multiplexers and bus structures - they have the unique ability to behave as elements which can be utilised to logically partition the circuit under analysis. • The objective of the methodology is to take advantage of any switches present in the circuit. • By using this knowledge to influence the selection of scan storage elements, the costs of partial scan design for the circuit can be reduced while achieving the maximum benefit.

47. Partial scan methodologies based on the analysis of circuit structure The situation before implementing the methodology

48. Partial scan methodologies based on the analysis of circuit structure The situation after implementing the methodology

49. Partial scan methodologies based on the analysis of circuit structure • A switch is a multiplexer or a bus whose control input line(s) are controllable during test, i. e. it should be possible to set and hold a given multiplexer or bus in a particular mode (I mode) while applying one or more clock cycles to the design. • From a test point of view both types of structures are seen to be equivalent.

50. Partial scan methodologies based on the analysis of circuit structure a) Multiplexer and b) bus used as switches