COE 405 Introduction to Digital Design Methodology

1. COE 405Introduction to Digital Design Methodology Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

2. Outline • Welcome to COE 405 • Digital System Design • Design Space and Evaluation Space • Digital System Complexity • Design Domains and Levels of Abstractions • Synthesis Process • Design Flow in Verilog • Simulation Process

3. Welcome to COE 405 • Catalog Description • Review of sequential circuits design and analysis, Data path and control unit design, Design with Hardware Description languages (HDL), Design with Field-Programmable Gate Arrays (FPGAs), Block interfacing. • Prerequisite: COE 202 Logic Design • Instructor Dr. Aiman H. El-Maleh. Room: 22/407-5 Phone: 2811 Email: aimane@ccse.kfupm.edu.sa • Office Hours

4. Course Objectives & Learning Ouctomes • Course Objectives: • Introduce students to the design methodologies of digital systems with special emphasis on FPGA implementations. • Course Learning Outcomes • Data Path and Control Unit design • Digital systems modeling using hardware description languages (Verilog HDL) • Simulation of digital systems • Synthesis and FPGA implementation of digital systems

5. Text Book • M. D. Ciletti, “Advanced Digital Design with the Verilog HDL,” (Prentice Hall), 2/e 2010.

6. Grading Policy • Discussions 5% • Assignments 15% • Quizzes 10% • Midterm 20% (Sat., Nov. 9, 1:30 PM) • Project 25% • Final 25% • Attendance will be taken regularly. • Excuses for officially authorized absences must be presented no later than one week following resumption of class attendance. • Late assignments will be accepted (upto 3 days) but you will be penalized 10% per each late day. • A student caught cheating in any of the assignments will get 0 out of 15%. • No makeup will be made for missing Quizzes or Exams.

7. Course Content • Introduction to Digital Design Methodology: Review of combinational logic design. Review of Sequential circuit design, Mealy versus Moore Machines, timing constraints, State minimization, State assignment. • Design of a digital system by partitioning it into a Data Path and Control unit: Design of DP and CU, Algorithmic State Machine (ASM) charts. • Introduction to logic design with Verilog: structural models of combinational logic, logic system, design verification and test methodology, propagation delay, truth table models of combinational and sequential logic with Verilog.

8. Course Content • Logic design with behavioral models of combinational and sequential logic: continuous assignment models, dataflow/RTL models, algorithmic based models. • Synthesis of combinational and sequential logic: Introduction to synthesis, synthesis of combinational logic, synthesis of sequential logic, synthesis of three-state devices and bus interfaces, synthesis of explicit state machines, synthesis of implicit state machines, synthesis of loops. • Design and synthesis of Datapath controllers. Block interfacing • Field Programmable Gate Arrays (FPGAs): FPGA technologies, Verilog based design flows for FPGAs, design and synthesis with FPGAs.

9. Digital System Design • Realization of a specification subject to the optimization of • Area (Chip, PCB) • Lower manufacturing cost • Increase manufacturing yield • Reduce packaging cost • Performance • Propagation delay (combinational circuits) • Cycle time and latency (sequential circuits) • Throughput (pipelined circuits) • Power dissipation • Testability • Earlier detection of manufacturing defects lowers overall cost • Design time (time-to-market) • Cost reduction • Be competitive

10. Digital System Design Cycle Design Idea  System Specification Behavioral (Functional) Design Pseudo Code, Flow Charts Architecture Design Bus & Register Structure Logic Design Netlist (Gate & Wire Lists) Circuit Design Transistor List Physical Design VLSI / PCB Layout Fabrication & Packaging

11. Architecture Design Control Unit Data Path Unit

12. Architecture Design Example • Problem:It is required to design a circuit to add two 8-bit numbers. The design must be as economical as possible in terms of hardware. • 8-bit Addition Possible Solutions: • There are numerous ways to design the above circuit, some of which are listed below. • Use an 8-bit ripple-carry adder • Use an 8-bit carry look-ahead adder. • Use two 4-bit carry look-ahead adders and ripple the carry between stages. • Use a 1-bit adder and perform the addition serially in 8 clock cycles.

13. Observations • Design involves trade-offs between • Cost • Performance • Testability • Power dissipation • Fault tolerance • Ease of design • Ease of making changes to the design. • Serial is cheap but slow, parallel fastest in terms of performance but most costly. • The different ways we can think of building an 8-bit adder constitutes what is known as designspace (at a particular level of abstraction). • Each method of implementation is called a point in the design space.

14. Design Space and Evaluation Space • Design space: All feasible implementations of a circuit. • Each design point has values for objective evaluation functions e.g. area. • The multidimensional space spanned by the different objectives is called design evaluation space.

15. Optimization Trade-Off in CombinationalCircuits

16. Combinational Circuit Design Space Example • Implement f = p q r s with 2-input or 3-input AND gates. • Area and delay proportional to number of inputs.

17. Digital System Complexity • Moore’s Law: Number of transistors that can be packed on a chip doubles every 18 months while the price stays the same.

18. How to Deal with DesignComplexity? • Hierarchy: structure of a design at different levels of description. • Abstraction: hiding the lower level details. • Design Hierarchy: • Design subsystems for simple functions • Compose subsystems to form the system • Treating subcircuits as “black box” components • Verify independently, then verify the composition • Top-down/bottom-up design

19. Bottom – UP Top – Down Design Hierarchy

20. Abstractions • An Abstraction is a simplified model of some Entity which hides certain amount of the Internal details of this Entity • Lower Level abstractions give more details of the modeled Entity. • Several levels of abstractions (details) are commonly used: • System Level • Chip Level • Register Level • Gate Level • Circuit (Transistor) Level • Layout (Geometric) Level More Details (Less Abstract)

21. Design Domains & Levels of Abstraction • Designs can be expressed / viewed in one of three possible domains • Behavioral Domain (Behavioral View ) • Structural/Component Domain (Structural View ) • Physical Domain (Physical View ) • A design modeled in a given domain can be represented at several levels of abstraction (Details).

22. Three Abstraction Levels of Circuit Representation • Architectural level • Operations implemented by resources. • Logic level • Logic functions implemented by gates. • Geometrical level • Devices are geometrical objects.

23. Levels of Abstractions & Corresponding Views

24. Design Methods • Full custom • Maximal freedom • High performance blocks • Slow • Semi-custom • Gate Arrays • Mask Programmable (MPGAs) • Field Programmable (FPGAs)) • Standard Cells • Silicon Compilers & Parametrizable Modules (adder, multiplier, memories)

25. Design vs. Synthesis • Synthesis • Process of transforming H/W from one level of abstraction to a lowerone. • Synthesis may occur at many different levels of abstraction • Behavioral or High-level synthesis • Logic synthesis • Layout synthesis • Design • A Sequence of synthesis steps down to a level of abstraction which is manufacturable.

26. Synthesis Process

27. Circuit Synthesis • Architectural-level synthesis • Determine the macroscopic structure • Interconnection of major building blocks. • Logic-level synthesis • Determine the microscopic structure • Interconnection of logic gates. • Geometrical-level synthesis (Physical design) • Placement and routing. • Determine positions and connections.

28. Circuit Synthesis • We usually design using register-transfer-level (RTL) Verilog • Higher level of abstraction than gates • Synthesis tool translates to a circuit of gates that performs the same function • Specify to the tool • the target implementation fabric • constraints on timing, area, etc. • Post-synthesis verification • synthesized circuit meets constraints

29. Physical Implementation • Implementation fabrics • Application-specific ICs (ASICs) • Field-programmable gate arrays (FPGAs) • Floor-planning: arranging the subsystems • Placement: arranging the gates within subsystems • Routing: joining the gates with wires • Physical verification • physical circuit still meets constraints • use better estimates of delays

30. HardwareDescriptionLanguages • HDLs are used to describe the hardware for the purpose of modeling, simulation, testing, design, and documentation. • Modeling: behavior, flow of data, structure • Simulation: verification and test • Design: synthesis • Two widely-used HDLs today • VHDL: VHSIC (Very High Speed Integrated Circuit ) Hardware Description Language (IEEE standard) • Verilog(from Cadence, now IEEE standard)

31. Design Automation & CAD Tools • Design Entry (Description) Tools • Schematic Capture • Hardware Description Language (HDL) • Simulation (Design Verification) Tools • Simulators (Logic level, Transistor Level, High Level Language “HLL”) • Synthesis Tools • Formal Verification Tools • Design for Testability Tools • Test Vector Generation Tools

32. Design Flow in Verilog • Define the design requirements • Describe the design in Verilog • Top-down, hierarchical design approach • Code optimized for synthesis or simulation • Simulate the Verilog source code • Early problem detection before synthesis • Synthesize, optimize, and fit (place and route) the design for a device • Synthesize to equations and/or netlist • Optimize equations and logic blocks subject to constraints • Fit into the components blocks of a given device • Simulate the post-layout design model • Check final functionality and worst-case timing • Program the device (if PLD) or send data to ASIC vendor

33. Simulation Process