200 likes | 586 Views
A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003. 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授. Outline. Introduction
E N D
A Dual-Slope Phase FrequencyDetector and ChargePumpArchitecture to Achieve FastLocking ofPhase-Locked Loop • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003 班級:積體所碩一 學生:林欣緯 指導教授:林志明 教授
Outline • Introduction • Proposed PLL Circuit Structure • Simulation and Measured Results • Conclusion • Reference
Introduction • Low-power consumption and low jitter have become the main concern in modern VLSI design. • The PLL needs to respond properly to unpredictable phase fluctuations, instant frequency shifts, and time-varying jitter.
Fine PFD circuit TSPC True Single Phase Clock 1. simple of structure 2. small dead zone
Simulated output waveforms of locked times in proposed PLL and conventional PLL
Conclusion • the proposed PLL has fast-lock, low-jitter and wide-operating frequency and can be used in modern high performance microprocessing system and clock data recovery system.
Reference • Kuo-Hsing Cheng, Wei-Bin Yang, and Cheng-Ming Ying, “A Dual-Slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop,” IEEE Transactions On Circuits And Systems—II: Analog And Digital Signal Processing, VOL. 50, NO. 11, NOVEMBER 2003