1 / 9

Through Silicon Vias

Through Silicon Vias. EECS713 Daniel Herr. Why Through Silicon Vias (TSVs)?. Demand for Faster, Smaller Chips Allows for Higher Density 3D chips Higher Density –> Higher Bandwidth Lead to significant Interconnect Length reduction vs. Edge Connected Multi-Chip Modules (MCMs).

jontae
Download Presentation

Through Silicon Vias

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Through Silicon Vias EECS713 Daniel Herr

  2. Why Through Silicon Vias (TSVs)? • Demand for Faster, Smaller Chips • Allows for Higher Density 3D chips • Higher Density –> Higher Bandwidth • Lead to significant Interconnect Length reduction vs. Edge Connected Multi-Chip Modules (MCMs) Multi-Chip Module (3)

  3. What is a TSV • Via through a Silicon Substrate • Generally Copper Via • Oxide Layer • Bump • Interposer Interconnect Multiple TSV Stack-up (1) TSV Layout (1)

  4. Modeling GSG TSV • Transmission Line Model • Resistance and Inductance behave as normal transmission line • Conductivity of the Silicon along with the oxide layer complicate the Model. Equivalent Circuit Model of TSV (1) Equivalent Circuit Model of Interposer (1)

  5. Channel Loss of TSV and Interconnect Effect of Interposer Silicon Conductance (1) Effect of TSV Silicon Conductance (1) Effect of Interposer Oxide Capacitance (1) Effect of TSV Oxide Capacitance (1)

  6. TSVs vs. Edge Connected MCMs • TSVs generally allow for shorter trace length • The Characteristic Impedance of TSV and interposer are frequency dependent. This can make it very challenging to impedance match. However; the Conductivity of the Silicon Substrate attenuates the reflection. • MCM has less loss than TSVs until the frequency is high enough. Characteristic Impedance vs Frequency (1) Channel Loss vs. Frequency (1)

  7. Substrate Coupling • Electro-Magnetic Coupling (What we’ve dealt with in class) • Because Silicon is a Semi-Conductor, the Conductivity of the Substrate is non-trivial. This leads to Parasitic Substrate Coupling TSV Test Setup (Side) (2) TSV Test Setup (Top-Down) (2)

  8. Effects of Substrate Coupling Voltage Transfer Function From Signal 1 to Signal 2 (2) (2) (2)

  9. References • 1: Measurement and Analysis of a High-Speed TSV Channel (Kim, Heegon; Cho, Jonghyun; et al.): http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/xpls/icp.jsp?arnumber=6268425 • 2: Trhough Silicon Via and 3-D Wafer/Chip Stacking Technology (Takahashi, Kenji and Sekiguchi, Masahiro): http://ieeexplore.ieee.org.www2.lib.ku.edu:2048/xpl/articleDetails.jsp?tp=&arnumber=6248929&queryText%3Dsilicon+high+speed+signals • 3: EECS713 Notes (Professor Allen)

More Related