JAZiO ™ Incorporated JAZiO

1. Digital Signal Switching Technology JAZiO™ Incorporated www.JAZiO.com

2. What is JAZiO Technology? • A new method of interchip I/O switching • At high data rate with low latency • With low power • At low cost • Effectiveness is due to using • Differential sensing with a single pin per bit • Built in timing • Based on looking for change-of-data first

3. Next bit time One bit time tRF tSU tHD Sharp Edges Cause: All information is transmitted during tRF (1/3 of bit time) Ground Bounce! Cross Talk! Ringing! EMI! High Power! The rest of the bit time is just wasted! Traditional Signal Driving

4. Next bit time One bit time VREF  0.8V Sensing Level Switching Level Large switching levels cause: Sensing level about 1/3 of switching level Ground Bounce! Cross Talk! Ringing! High Power! The rest of the switching level is just wasted! Pseudo Differential Signal Sensing

5. JAZiO Solution • JAZiO has invented a system which • Achieves very high performance • Has edges which can take the whole bit time • Uses differential sensing with very low signal levels • Yet has only 1 pin per data signal

6. What’s the Secret? A Re-think • For each data signal, there is either a change or no-change from the previous bit time • Traditional systems are good on no-change but bad on change • JAZiO looks for change first and then adjusts if no-change occurs • For JAZiO the decision binary is change or no-change rather than high or low voltage

7. VTR Provide alternating Voltage/Timing References switching at the data rate VTR 3 7 Data is driven coincidentally with Voltage/Timing References Data Input 1 5 2 6 8 4 8 different combinations of VTR and Data Input One Bit Time Next Bit Time A Dual Comparators are used VTR Data Input Data Output Steering Logic B VTR JAZiO Solution In cases 1 and 6 Comparator A makes a differential comparison In cases 2 and 5 Comparator B makes a differential comparison In the other four cases Data Input does not change

8. Steering Logic The trick is to know how to select between Comparators A and B and what to do when Data Input does not change

9. A out in VTR XOR in Data Output Data Input B in out in VTR XOR VTR SL VTR SL VTR Steering Logic • Generate Steering Logic signals (SL and SL) • Use them with Data Output from previous Bit Time to select between Comparators A and B

10. Data Input Data Input VTR XOR SL Initialization or Receiver Enable Data Output SL XOR VTR 55 Small Transistors Per Bit No PLL/DLL Required No die size penalty!!!

11. The receiver cell is: 22um x 55um (Including routing channels) The pad cell is: 70um x 80um

12. A out in VTR XOR in Data Output Data Input B in out in VTR XOR VTR SL Determine no-change and switch to Comparator B VTR SL VTR First Look for change Data Input  0.5V VTR Time Domain Decision is made in the Time Domain rather voltage domain

13. A VTR out in SL XOR-A Data Output in Data Input (High) B in VTR out in SL XOR-B Bit Time But! The handoff from Comparator A to B is smooth since both of them want to drive Data Output high After the handoff, Comparator B is ready to make the next differential comparison Since Comparator A is selected its high value causes Data Output to remain high The No-Change Case Comparator A is selected and as the differential on its inputs disappears the output remains high temporarily However, Comparator B is gaining a differential and its Output becomes a solid high But eventually the XORs will switch And Comparator B will be selected

14. Data Output 17 Data Output 9 Data Output 8 Data Output 0 XOR XOR SL SL XOR XOR XOR XOR XOR XOR Bits 10-16 Bits 1-7 SIGNALS FROM PADS VTR VTR Data Input 0 Data Input 8 Data Input 17 Data Input 9 18 JAZiO™Receivers

15. 10G • Slower edges • Lower switching levels • Reduced slew rate JAZiO™ Better JAZiO™ 1G JAZiO™ RDRAM Data Rate per Pin (b/S) DDR SDRAM-100 100M SDRAM-66 EDO-33 10M 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Slew Rate (V/nS) Data Rate vs Slew Rate Comparison Higher Performance at Lower Power with Higher Robustness

16. Applying JAZiO Technology • JAZiO is the physical I/O layer only • JAZiO provides no protocol • Works with any protocol • Like steel belted radial tires that work for Honda Civic, Ferrari Sports Car, or Ford Explorer • Easy to use • No die size penalty • No PLL/DLL or special semiconductor technology • Low Power • Can be used anywhere that fast switching or low power is useful

17. JAZiO for DRAM • JAZiO Technology can be applied to scaled-up versions of existing protocols like DDR or RDRAM • Or new protocols can be developed to match JAZiO’s low latency and high bandwidth to reduce pins and increase parallelism

18. 1GHz CPU L3 L3 L3 L3 BSB All scalable to 2x frequencies CPU CPU CPU CPU FSB CONTROLLER DRAM 1GHz Data Rate Quad Processor Module Quad Processor Module I/O 2GHz Interprocessor Communication (Scalable to 4GHz) Quad Processor Module Quad Processor Module 16-Wide MP Server with 2GHz FSB & BSB

19. FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA FPGA Hardware Emulation Narrow, very high speed JAZiOTM interconnect that allows many FPGAs to appear as a massive logic array

20. Notebook / Internet Appliance JAZiO™ SOC DRAM Power consumed in the memory interface is reduced due to low switching levels of VTT=1.0v and VLOW=0.5v Pavg = K•Dv•VTT K a (Cf+1/Rt) Therefore Power Ratio = (0.5v•1)/(0.8v•1.8) » 1/3 When compared to existing pseudo differential with VTT=1.8v, Dv=0.8v, similar load capacitance, operating frequency and termination resistance Small swing and slower transition time reduces EMI, allowing it to be under FCC limits for higher frequency operation

21. How Can JAZiO Be Used? • JAZiO is “essentially” an Open Standard • All technology is publicly visible w/o NDA • Anyone can see it, study it, simulate it, design it in, build test chips, build prototypes, etc • Just don’t sell products without licensing it • A JAZiO demonstration chip is in design by Micro Magic, Inc – a JAZiO Design Services partner

22. Conclusion • JAZiO uses lower levels and slower edges • Achieves high performance, low power, high robustness • JAZiO technology is fundamentally different from traditional methods • Time domain rather than voltage domain • Look for changefirst • Change vs No-change rather than High or Low • JAZiO is available to everyone at low cost and applies to any application