System Verilog Randomization and IPC

1. IEP on Design Verification and Hardware Security NIT, Rourkela System Verilog Randomization and IPC

2. OUTLINE • Randomization • Randomization Constraints • Random System Methods • Inter-process Communication • Semaphore • Mailbox • Event • Assertions. • Functional Coverage • Example

3. Randomization • SystemVerilog randomization is the process of generating random values to a variable. • Verilog has a $random method for generating the random integer values. This is good for randomizing the variables alone, but it is hard to use in case of class object randomization. • rand: - Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range. • randc: - randc is random-cyclic. For the variables declared with the randc keyword, on randomization variable values don't repeat a random value until every possible value has been assigned. • In order to randomize the object variables, the user needs to call randomize() method. • object.randomize();

4. Randomization Example Courtesy: www.verificationguide.com

5. Randomization methods • constraint_mode(): is a method to control whether a constraint is active or inactive. All constraints are initially active. • rand_mode(): - is used to disable the randomization of a variable declared with the rand/randc keyword.rand_mode(1) means randomization enabled rand_mode(0) means randomization disabled The randomization enables/disable status of a variable can be obtained by calling vairble.rand_mode().  • randomize() with: This construct allows the declaration of inline constraints at the point where the randomize() class method is called. The original constraints in the class definition does not have to be changed. • pre_randomize()/post_randomize(): Every class contains built-in pre_randomize() and post_randomize() tasks, that are automatically called by randomize() before and after it computes new random values.

6. Randomization Constraints • Constraint blocks are class members like tasks, functions, and variables • Constraint blocks will have a unique name within a class • Constraint blocks consist of conditions or expressions to limit or control the values for a random variable • Constraint blocks are enclosed within curly braces { } • Constraint blocks can be defined inside the class or outside the class like extern methods, constraint block defined outside the class is called as extern constraint block Courtesy: www.verificationguide.com

7. Randomization Example Courtesy: www.verificationguide.com

8. Pre-randomize and Post randomize Courtesy: www.verificationguide.com

9. “inside” operator in randomization Courtesy: www.verificationguide.com

10. Inheritance in Randomization Courtesy: www.verificationguide.com

11. Weighted Distribution in randomization • “src” gets the value 0, 1, 2, or 3. The weight of 0 is 40, whereas, 1, 2, and 3 each have the weight of 60, for a total of 220. The probability of choosing 0 is 40/220, and the probability of choosing 1, 2, or 3 is 60/220 each. • “dst” gets the value 0, 1, 2, or 3. The weight of 0 is 40, whereas 1, 2, and 3 share a total weight of 60, for a total of 100. The probability of choosing 0 is 40/100, and the probability of choosing 1, 2, or 3 is only 20/100 each. Courtesy: System Verilog for Verification, Chris Spear, Springer Publication

12. Implication operator in randomization • The implication operator can be used to declaring conditional relations between two variables. Implication operator is denoted by the symbol : “->”. Courtesy: www.verificationguide.com

13. Functions in Constraints Courtesy: www.verificationguide.com

14. Unique Constraints SV support “unique” keyword in randomization and variables defined with this keyword will get unique values during randomization. This is applicable to variables and array elements. Courtesy: www.verificationguide.com

15. Solve Before Solve before is used in the constraint block to specify the order of constraint solving. This property is helpful when variables are dependent. Courtesy: www.verificationguide.com

16. Bidirectional Constraints Courtesy: www.verificationguide.com

17. Inter Process Communication: Semaphore Semaphore is a SystemVerilog built-in class, used for access control to shared resources, and for basic synchronization. Processes must wait until a sufficient number of keys are returned to the bucket. Semaphore methods: - SV support built-in classes for semaphores: - 1. new (): create semaphores with a specified number of keys. Example: semaphore_name = new (no. of keys); 2. get (): get a key or keys to semaphore. Ex: -semaphore_name.put () or semaphore_name.put(no. of keys); 3. put(): return the semaphore key or keys Ex: - semaphore_name.get () or semaphore_name.get (no. of keys); Courtesy: www.verificationguide.com

18. Mailbox • A mailbox is a communication mechanism that allows messages to be exchanged between processes. • Based on the sizes mailboxes are categorized as: - • bounded mailbox • unbounded mailbox • A bounded mailbox is with the size defined. Unbounded mailboxes are with unlimited size. • Mailbox types: - There are two types of mailboxes,Generic Mailbox • Parameterized mailbox Mailbox methods: SV supports following mailbox methods:- new (); create a mailbox put (); place a message in a mailbox try_put (); Try to place a message in mailbox without blocking get (); or peek (); retrieve a message from a mailbox num (); returns the number of messages in mailbox. try_get (); or try_peek (); try to pull a message from mailbox without blocking.

19. Mailbox Mailbox is used to communicate between generator and driver. Generator class will generate the packet and put into mailbox and driver class access the generated packet from the mailbox. Courtesy: www.verificationguide.com

20. Events • Events are static objects useful for synchronization between the process. Events operations are of two staged processes in which one process will trigger the event, and the other processes will wait for an event to be triggered. • SystemVerilog events act as handles to synchronization queues. thus, they can be passed as arguments to tasks, and they can be assigned to one another or compared. • -> : -Named events are triggered via the -> operator. Triggering an event unblocks all processes currently waiting on that event. •  ->>:Non-blocking events are triggered using the ->> operator. • @ operator: - wait for an event to be triggered is via the event control operator, @. • Ex: - @(event_name.triggered);

21. Events Courtesy: www.verificationguide.com

22. Mailbox • A mailbox is a communication mechanism that allows messages to be exchanged between processes. • Based on the sizes mailboxes are categorized as: - • bounded mailbox • unbounded mailbox • A bounded mailbox is with the size defined. Unbounded mailboxes are with unlimited size. • Mailbox types: - There are two types of mailboxes,Generic Mailbox • Parameterized mailbox Mailbox methods: SV supports following mailbox methods:- new (); create a mailbox put (); place a message in a mailbox try_put (); Try to place a message in mailbox without blocking get (); or peek (); retrieve a message from a mailbox num (); returns the number of messages in mailbox. try_get (); or try_peek (); try to pull a message from mailbox without blocking.

23. Functional Coverage • There are 4 places where functional coverage points can be coded in a verification environment, and they can be classified as: - • 1. Functional coverage points on which variables used in randomization: - • These set of coverage points are coded in class which is instantiated very near to the randomization and it is before actual BFM/driver to DUT. • Assume for some reason, BFM/Driver is not able to send randomized object to DUT, even then functional coverage gets updated. This is not acceptable. • 2. Functional coverage points are sampled at input interface of DUT: - • These set of coverage points are coded in class which is instantiated inside a input monitor or coverage class itself will have ability to sample the DUT input signals. • This is perfect for having functional coverage on stimulus that DUT is being driven with.

24. Functional Coverage • 3 : Functional coverage points which sample internal DUT states: - • These set of coverage points are coded in class which is instantiated as standalone class, and it monitors the internal states of DUT, like FSM states, or some registers. SVA will be useful in achieving these coverage points. • 4 : Functional coverage points which sample output interface of DUT: - • These set of coverage points are coded in class which is instantiated inside a output monitor or coverage class itself will have ability to sample the DUT output signals.

25. Functional Coverage Courtesy: www.verificationguide.com

26. Covergroup A covergroup can contain following constructs: - • clocking event : Defines the event at which coverage points are sampled. If the clocking event is omitted, users must procedurally trigger the coverage sampling. • coverage points : A coverage point can be a variable or an expression. • cross coverage : Coverage group can also specify cross coverage between two or more coverage points or variables. • coverage options : This are used to control the behaviour of the covergroup.

27. Cover group • Cover Group Inside a Class: - • Covergroup can be embedded inside a class, interface, or module. When embedded inside a class, it allows to generate coverage on subset of class properties. • Important difference between a covergroup in module and covergroup in class is that, it is optional to create the instance of covergroup in class. • An embedded covergroup can define a coverage model for protected and local class properties without any changes to the class data encapsulation.

28. Ones Counter Courtesy: www.testbench.in

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30. Ones Counter_TestBench Courtesy: www.testbench.in

31. Ones Counter_TestBench Courtesy: www.testbench.in

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